# What causes the common mode gain in MOS differential amplifier

I went through many of the past questions in this forum and also a lot of other sites but none answered my question, so I made up my mind to post it here.

What exactly causes the common mode signal to appear at the output side ? I know that the transistors are not symmetric and this causes an offset but assuming the transistors are all symmetric, what causes the common mode signals not to be rejected completely ?? I think this has to do with the tail current source not being ideal but how does this exactly affect ??

• I think this has to do with the tail current source not being ideal Indeed that is it. Now make a small signal model for the common mode signal, so V1 = V2 and determine Vo. If M5 has an infinite Rds the transfer will be different from when it is not infinite. Commented Jun 3, 2016 at 11:19
• @FakeMoustache Ahh okay so you mean in a large signal point of view there will not be any common mode amplification but in a small signal view there is ? And Yes I did see a derivation in which they split M5 into 2 transistors and then calculate the transfer function which comes out to be Vo/Vic = -1/(R5ds*2*gm3) . But is there an intuitive way to understand this ?? Commented Jun 3, 2016 at 11:48
• The gain is completely a function of the bias current as this sets the complete flux through the system. If you draw a band diagram, you'll see that you have "source follower" between the bias and one side of the input pair. The voltage gain can be seen as the band diagram field balance. The best descriptions for intuition that I know are in Carver Mead's "Analog VLSI and Neural Systems" or Shih-Chii Liu's "Analog VLSI" book. You can use the large/small signal models, but those are more constrained. If you push though the physics, you'll find that it'll serve you well in every scenario. Commented Jun 3, 2016 at 13:03
• so you mean in a large signal point of view there will not be any common mode amplification but in a small signal view there is I never wrote that because that is not true. Large signal behaviour is more complex than SS. First understand SS then maybe look at LS. Commented Jun 3, 2016 at 13:15
• There is a simpler and more intuitive way to understand the CMM behaviour. If V1 and V2 both go up dV in voltage, the drain of M5 also goes up a little bit less than dV (part of dV ends up in Vgs of M1, M2). When M5 is non-ideal, it has an Rds. Then the tailcurrent will increase with dV/Rds. This goes to mirror M3+M4. If this mirror is ideal, v0 would not see the CMM. But if there is a slight imbalance the current difference Id_M4 - Id_M2 is pushed into the output node. Multiply that with the Rout at the output and you have your CMM gain. Commented Jun 3, 2016 at 13:24

A common mode gain is the result of two things. The finite output resistance of the current source (M5) and an unequal current division between M1 and M2.

The finite output impedance is a result of the transistor's output resistance rds and the parasitic capacitors at the drain of M5. The result is that any change of the common voltage results in a change of ISS.

Assuming only a common mode voltage and no differential voltage the change of the current ISS splits between M1 and M2. In practice M1 and M2 are slightly different due to mismatch, the current won't split equally and a differential current results that is converted into an output voltage.

Even for perfectly matched transistor a slight imbalance can be found, M1 has a diode-connected load and M2 has a current-source load. The impedance when looking into the sources of M1 and M2 will be slightly different due to this asymmetry. Again a differential current will result.

Update: In some textbooks the common mode rejection is derived for a fully differential structure with perfect matching. Then the common-mode rejection is calculated as the ratio of common-mode ouput to common-mode input.

This gives the well known result Acm ~ RD / (2 rds5)

The circuit shown in your post is singled ended and therefore another approach is required.

• Sure I see your point ! So in a way you mean even if there is pure symmetry the design by default poses a means to not completing reject the common mode signals. But then I dont understand why many books point out to the fact that M5 since its not ideal is the main reason for the issue. Rather they should be pointing out to the diode connected deisgn as the main reasons for the problem. Commented Jun 3, 2016 at 15:07
• @Bhuvanesh N -- I've made an upate. Commented Jun 3, 2016 at 15:40

As @Mario mentioned, if we assume M3 and M4 are symmetrical and have a saturation resistance of rds and M5 has an on resistance of rds5, then the common mode gain is rds/(1/gm + 2*rds5).