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There has been a lot of research around GaN transistors, proving that they have a very low on-resistance, low gate-charge and are very effective at high temperatures.

So why are we still mostly producing Si transistors? Even if the GaN transistor is more expensive in production, it surely must compensate if it's used in IC's?

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    \$\begingroup\$ FakeMoustache's answer is excellent; however, you also need to think about cost. Si is cheap. I can take your masks from Si, and just change the wafer to SiGe to get 10% speed up at the same power, but the cost is 25% more for the wafer. From there I can go to Sapphire wafers, etc. You are stuck in a commodity market. If you don't have price constraints, you get to do all sorts of neat things that will not be seen in the mainstream. SiCMOS is not fast, but it sure is cheap. \$\endgroup\$ – b degnan Jun 5 '16 at 10:33
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    \$\begingroup\$ @bdegnan You should add this as an answer. Comments aren't for answers, and don't last forever. \$\endgroup\$ – Insane Jun 5 '16 at 17:51
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I've been using GaN extensively since 2013 or so, primarily for a niche application that can easily benefit from one huge advantage GaN has over Si -- radiation tolerance. There's no gate-oxide to puncture and suffer from SEGR, and public research has shown the parts living past 1MRad with minimal degradation. The small size is amazing as well -- in the size of maybe a quarter or two (the coin), you can implement a 10A+ DC/DC converter with ease. Coupled with the ability to purchase them with leaded-solder bars, and some third-parties packaging them in hermetically sealed packages, they are the future.

It's more expensive, and "trickier" to work with. There is no gate-oxide, just a metal-semiconductor junction, so the gate drive voltage is highly restrictive (for enhancement mode as built by EPC) -- any excess voltage will destroy the part. There are only a handful of publicly available gate drivers right now -- folks are just now starting to build more drivers and give us more options than the National LM5113. The 'canonical' implementation you'll see around is the BGA LM5113 + LGA GaN FETs, because even the bond-wires in other packages add too much inductance. As a reminder, here's where that ringing comes from:

enter image description here

EPC's eGaN devices utilize a 2DEG and can be classed as a HEMT in our applications. This is where a lot of their stupidly low RDS(on) comes from -- it's usually in the single-digit milliohms. They have incredibly fast speeds, which means you have to be very aware of Miller-effect induced turn-on. Additionally, as mentioned above, parasitic inductances in the switching loop become much more critical at these speeds -- you actually have to think about your dielectric thicknesses and component placement to keep that loop inductance low (<3nH is doing alright, IIRC, but as discussed below, it can/should be much lower), as also seen below:

Illustration of the 2DEG enter image description here

For EPC, they are also built at a conventional foundry, lowering costs. Other folks include GaN systems, Triquint, Cree, etc -- some of those are specifically for RF purposes, whereas EPC primarily targets power conversion / related applications (LIDAR, etc.). GaN is natively depletion-mode as well, so folks have different solutions for making them enhancement, including simply stacking a small P-channel MOSFET on the gate to invert its behavior.

Construction of eGaN Device

Another interesting behavior is the "lack" of reverse recovery charge, at the expense of a higher-than-silicon diode drop when in that state. It's kind of a marketing thing -- they tell you that "because there are no minority carriers involved in conduction in an enhancement-mode GaN HEMT, there are no reverse recovery losses". What they kind of gloss over is that V_{SD} is generally up in the 2-3V+ range compared to 0.8V in a Si FET -- just something to be aware of as a system designer.

I'll touch on the gate again as well -- your drivers basically have to keep a ~5.2V bootstrap diode internally to prevent cracking the gates on the parts. Any excess inductance on the gate trace can lead to ringing that will destroy the part, whereas your average Si MOSFET usually has a Vgs around +/-20V or so. I've had to spend many a hour with a hot-air gun replacing a LGA part because I messed this up.

Overall, I'm a fan of the parts for my application. I don't think the cost is down there with Si yet, but if you're doing niche work or want the highest possible performance, GaN is the way to go -- the winners of the Google Little Box Challenge used a GaN-based power stage in their converter. Silicon is still cheap, easy to use, and people understand it, especially from a reliability POV. GaN vendors are going to great lengths to prove their device reliability figures, but MOSFETs have many decades of lessons-learned and reliability engineering data at the device physics level to convince folks that the part isn't going to burn out over time.

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    \$\begingroup\$ Also side note, not trying to shill for EPC, it's simply the vendor whose topology (enhancement-mode GaN transistors for power applications) I'm most familiar with. There are others as well -- Cree, GaN Systems, etc. \$\endgroup\$ – Krunal Desai Jun 6 '16 at 0:20
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    \$\begingroup\$ The 3 nH figure is interesting - some of the really fast circuits EPC was showing off had 0.4nH loop inductance. They also said the gate voltage sensitivity decreased with their Gen 4 devices.... I don't play with GaN, mainly SiC so I don't have immediate experience. \$\endgroup\$ – W5VO Jun 6 '16 at 3:42
  • \$\begingroup\$ I'm remembering some of their earlier papers / layout guides for the Gen1/Gen2 devices I think where they were in that range...0.4nH is nuts, how thin was the L1/L2 dielectric? I know it gets easier if you use their integrated parts as well (shrunken SW node). \$\endgroup\$ – Krunal Desai Jun 6 '16 at 3:56
  • \$\begingroup\$ I think 4-8 mils was the thickness (trying to remember), though they weren't using half-bridge parts in this example. This was part of their studies of layout topologies, and they weren't using a combined device. I remember thinking that GaN layouts were going to make board fab houses rich from all the special requirements. \$\endgroup\$ – W5VO Jun 6 '16 at 5:17
  • \$\begingroup\$ The integrated parts (like the EPC2100, IIRC) definitely do -- you have to use microvias in order to use those parts, no other way unless you've got a house that can handle some impressive aspect ratios w/ micro-drilling. \$\endgroup\$ – Krunal Desai Jun 6 '16 at 12:00
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it surely must compensate if it's used in IC's

Well no, it does not for several reasons:

  • GaN transistors cannot easily be made in today's IC manufacturing processes
  • Not every application needs the fastest transistor
  • Not every application needs the lowest on resistance
  • Not every application needs the high temperature behaviour
  • GaN transistors cannot be made as small as the smallest MOS transistor

Compare it to SiGe (Silicon Germanium) which has been available for many years. It has faster (bipolar) transistors. Is it used everywhere? No, because few ICs use bipolar transistors. 99% of today's ICs use CMOS transistors only making SiGe manufacturing processes a niche application.

The same is true for GaN, it's only useful for Power transistors. ICs generally have no need for this kind of power transistors.

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GaN Integrated Circuits

Currently GaN is not in a position to overtake silicon in typical IC applications as the lithography and processing is not as mature as silicon, and CMOS GaN is still in early research. Multiple transistor integration is already possible with GaN, but the primary application is power switching because that is where most of the benefits can be realized. For a large number of circuits, a successful GaN implementation is not possible or only has niche uses. A GaN microcontroller is not something achievable with current technology, for example.


However, in power circuits, there are many advantages that you can realize with current GaN devices:

Faster Switching (Lower RDS(on) for a given die area )

With great power switching speed comes great responsibility to manage parasitic inductance. You will see adverse circuit behavior with loop inductances above 1 nH, and it's very hard to avoid that much inductance in your layout. For many silicon circuits, you can get away with relative murder. In order to get the most out of these transistors, you must pay attention to all aspects of your power converter layout far beyond the level of detail typically required by silicon designs.

Smaller packages

The packaging is also smaller, with EPC selling what are essentially solder-bumped die that you directly reflow onto a PCB. For example, this 40V, 16mΩ, 10A device is 1.7mm x 1.1mm, or a bit bigger than the size of an 0603 resistor. Handling and processing must be prepared for BGA-style techniques instead of larger SMT parts or through hole.

Good temperature behavior

And good temperature operation is useless if you need to have a standard silicon part next to it to control it.

Low gate drive voltage

The low gate voltage drive (typically 5V for EPC parts) is also matched with a low maximum gate voltage (-4V to +6V Vgs for the part linked above). This means that your gate driver must be rock steady in order to keep the device from damaging itself, and (again) your layout must be good. This has gotten better, but is still a concern.

There is a lot of desire to see the benefits of GaN as a drop-in replacement for a silicon part. At this rate, the added work needed to ensure stable and safe operation, and the work needed to take advantage of the faster switching speed means that it will not simply replace silicon FETs in old designs. As FakeMoustache mentions, you don't always need top performance (and sometimes the transistor isn't even the weak spot).

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GaN is becoming useful in RF amplification and power conversion (switching power supplies). In the latter case it needs much less cooling than Si, in the former it can run faster.

But for the RF amplification uses, it's not just competing with Si, it's competing with GaAs (e.g. MMICs) and SiGe. For power conversion, SiC is also becoming interesting.

But it's not just about the cost and competing technologies. The best GaN devices for both on-resistance and switching speed are HEMTs. GaN HEMTs are normally-on devices¹ requiring a negative gate bias to turn them off. This adds cost and complexity to the system, and also means that a control-circuit failure can lead to the transistor failing on, which is "interesting" if you're dealing with things like HVDC.

GaN has to be grown on a hetero-substrate, which makes growth harder (further adding to the cost). Despite years of research this still affects the material quality of the epilayers, with implications for the performance/lifetime tradeoff.

So GaN is likely to be a very useful technology for certain niche applications, becoming more mainstream if it develops faster than some of the rival technologies.


¹I have worked with some GaN HEMTs on Si substrates that have a positive threshold voltage, but I don't think any have yet made it to the market.

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So why are we still mostly producing Si transistors? Even if the GaN transistor is more expensive in production, it surely must compensate if it's used in IC's?

What makes you believe that "it surely must compensate"? It definitely is not the case.

The (German) Wikipedia-article of GaN says that the main problem in producing GaN-based devices was and still is the difficulty of producing large single crystals. The article also shows for example a single crystal whose length is just 3mm (Even if it might be possible to produce larger ones it won't be much larger).

In contrast to that it is possible to produce Si single crystals whose diameter is almost half a meter (ca. 500mm) and whose length is a multiple of that.

Just this huge difference in obtainable single crystal size makes clear that mastering Si technology is much more advanced than GaN Technology.

And there are more aspects than single crystal size.

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  • \$\begingroup\$ I believed this because I saw some graphs displaying the dissipation energy when being switched from on to off and vice versa. I didn't realise this was only for power transistors. \$\endgroup\$ – Casper Vranken Jun 6 '16 at 9:02
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The layout problems mentioned in earlier answers are becoming less relevant with manufacturers integrating the driver and the transistor in a single package, thus circumventing the problem of gate loop and common source inductance. So, to a large extent, the question should be: "By when are we using GaN everywhere?"

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