I am researching single board computers with the hope of designing on at the end of this, I am at the stage of DDR3, but can't find any good info on routing ddr3, regarding what traces need to be matched, and so on. Which traces need to be matched? I am assuming it's the DATA traces, and any traces that take data that needs to be in sync, would I be correct in thinking this? Or would it be better to match them all to avoid the chance of missing something or running into issues.
Datasheet: http://www.alliancememory.com/pdf/ddr3/4GB-AS4C256M16D3L.pdf

  • \$\begingroup\$ What other traces are there? I mean, obviously, the address lanes have the same problems as the data in / out lines, so I don't think you're asking about that. Power supply lines are pretty much effectively lengthless (since \$\lambda_\text{DC}\approx\infty\$) or your power supply is bad, and then there's stuff like the I²C lines for SPD, which serve a totally unrelated purpose. \$\endgroup\$ – Marcus Müller Jun 5 '16 at 13:14
  • \$\begingroup\$ @Marcus Müller Are you quite certain that you can model power for high-frequency electronics as an ideal DC draw? I would be quire concerned by the rise times. \$\endgroup\$ – AndrejaKo Jun 5 '16 at 13:34
  • \$\begingroup\$ @AndrejaKo jup, that's why I said that it should be ideall lengthless. I can see my wording being more than a little confusing: so yeah, as usual, place your power supply close, using thick lines, sufficient decoupling, yadda yadda. Don't match its length to that of the data lines, that would be hazardous. If your power supply lines effective length becomes significant to the voltage oscillations you see on the power line, you're doing something wrong. \$\endgroup\$ – Marcus Müller Jun 5 '16 at 13:44
  • \$\begingroup\$ When in doubt, always reference your chip vendor's documentation! While there are some things that are covered by JEDEC spec, it is sufficiently complicated that doing an Intel-based DDR3 design vs. an FPGA/SoC-based DDR3 design will have differing requirements. \$\endgroup\$ – Krunal Desai Jun 5 '16 at 21:53

Generally speaking, there are two sets of signals that connect to a DDR3 memory:

  • Address and control signals, which flow from the memory controller to the memory chip(s), accompanied by a reference clock.

  • Data signals, which flow in both directions between the controller and the memory, accompanied by a separate strobe signal.

The trace lengths within each of these groups should be matched, but the matching between the two groups is not as critical.

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  • \$\begingroup\$ What would be an acceptable amount of tolerance in MM? for trace lengths. \$\endgroup\$ – Alex Jun 6 '16 at 9:20
  • \$\begingroup\$ Read the datasheets for all of the chips involved! Sometimes you need to account for package internal delays, too -- sometimes not. \$\endgroup\$ – Dave Tweed Jun 6 '16 at 10:54
  • \$\begingroup\$ Well, I did that. And from what I can see, it includes nothing about it. \$\endgroup\$ – Alex Jun 6 '16 at 11:43
  • \$\begingroup\$ Sometimes it's implicit in the timing specs. The clock period is already short, and the setup and hold times use up a significant fraction of it. Any skew you introduce with mismatched trace lengths (to the tune of 6-7 ps per mm) just eats further into your timing budget. How much of this you can tolerate depends on how fast you intend to run the system relative to the chip capabilities. \$\endgroup\$ – Dave Tweed Jun 6 '16 at 11:52

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