# Square wave filtering with d-flip flop

I have a square wave (1st line), I want to skip every odd impulse, and output every even one without change, as shown in the second line.

Is this different from frequency division? What is the proper name for such circuit? Can it be done with double d-flops, like 4013?

• D flip-flop and an AND gate. Jun 6, 2016 at 3:06
• Indeed. D flop setup as a toggle with Q-not fed back to D. Clocked on input positive edge. Jun 6, 2016 at 4:04
• it might be possible with just the 4013, set it up as a divide by two circuit and then disconnect the positive supply! CMOS is funly like that :) Jun 6, 2016 at 4:49

user2943160's answer is essentially correct, but not perfect. As he states, there will be a glitch (runt pulse) produced when a pulse which will be swallowed comes along. In this case when the input goes high, the FF output persists high for the propagation delay of the FF, and this will produce a pulse. Likewise, the next pulse which comes along will be shortened by the FF propagation delay.

There are two ways to deal with this. Assuming the FF has a propagation delay of two inverters,

simulate this circuit – Schematic created using CircuitLab

will work, but it does have the possible drawback that it requires that the FF propagation delay be accurately known. If this is not the case, a more general approach is to operate the FF on the falling edge of the pulse.

simulate this circuit

• so, i need d-flop, AND and 2 NOTs. Is there a way to minimize it to 2 4000 series ICs? Jun 6, 2016 at 23:01
• @darvin - sure - use a quad NAND to create both the NOTs and the AND. And any dual flip-flop will have Q and Q* outputs, so you won't need the feedback inverter. And you don't need a D type, since a JK will also do the job. A T flip-flop will also work. Jun 6, 2016 at 23:20

This is a specific type of frequency division. It appears that the term Pulse-swallowing counter is already taken by a different and very specific counter.

Using a basic DFF with an AND gate (NOT is provided by the DFF's inverted output), you can achieve the desired result:

simulate this circuit – Schematic created using CircuitLab

However, there will be some propagation delay that may produce glitches due to the propagation delay through the flip-flop.

Follow-up: there doesn't seem to be a way to make an AND gate with the set/reset signals of the 4013. External logic will be required to have the half-frequency square wave retain the original pulse shape.

• I'm not convinced that pulse swallowing is incorrect here, the stub page on wikipedia can hardly cover all usages of the term. Jun 6, 2016 at 7:11