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Problem:

my photo diode recieves pulses of width 10ns-150ns and repeating at rate of 1Hz-50KHz

the current from photo diode depending on incident light can go from 10nA-100mA, so i have two photo diodes to cover the dynamic range, what i want to do is limit the current from a photo diode to 5mA lets say in one channel

Approach Followed:

in search i found some thing similar to my need here

enter image description here

the patent claims: in the picture the current sources 30 and 38 are the maximum current at which the TIA saturates, as soon as the TIA saturates, the schottky bridge isolates the TIA from source,

i have less idea whether the patent circuit can work for pulsating current, but when i tried the results did not show any difference

enter image description here

if you think this is not the right circuit for my application, kindly let me know if any other approach i can follow to put my TIA away from excess current than saturation,

EDIT: with constructive comments i have changed the FET to p-channel which worked like charm, but i am not very clear of

how to select the schottky diode and also the pJFET for much better response

if you see below schematic i have given a trail of pJFET of all available with LTspice, and same with schottky

Result after change in type of FET to PJFET, you can clearly see the input current being more than current sources

enter image description here

How to realize 30 and 38 on practical circuit ?, how can i create stable dc current sources ?

EDIT:

How to realize 30 and 38 on practical circuit ?, how can i create stable dc current sources ?

Work Done:

for realizing these current sources i have chosen a 2 terminal programmable current source from LT, which solved the problem to an extent, but few problems still exist

Modified Design:

enter image description here

Results with 10uA pulsating input:

enter image description here

Results with 100mA pulsating input:

enter image description here

further work:

even though the excess current is limited i want the waveform not to distort, kindly point out flaws in the design

PS: an unclear but similar question present here

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  • \$\begingroup\$ Why are you doing this? What breaks if the current is greater than 5 mA? (You could limit the opamp output voltage.) \$\endgroup\$ – George Herold Jun 6 '16 at 14:09
  • \$\begingroup\$ What happens if you reverse your input current? Also, you might need to use "real" current sources (current mirrors) rather than ideal current sources for I2 and I3 to avoid this circuit going crazy. Think about what happens if I1 produces 15 mA. How is KCL satisfied without something else going nuts (like a didoe going into reverse breakdown)? \$\endgroup\$ – The Photon Jun 6 '16 at 16:20
  • \$\begingroup\$ Now I read the patent (esp. paragraph 0024) and I am pretty sure you need to reverse the polarity of your input source to make the circuit work as expected. \$\endgroup\$ – The Photon Jun 6 '16 at 16:29
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    \$\begingroup\$ Changing the question after someone has taken time to answer just makes the site less useful for future readers, and discourages people from answering your question. If you come up with new questions after getting an answer to your posted question, consider making a new question post. \$\endgroup\$ – The Photon Jun 8 '16 at 17:18
  • \$\begingroup\$ I thought of putting complete problem statement at one place.ok will post a new one \$\endgroup\$ – kakeh Jun 9 '16 at 1:25
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From the patent you cited,

[0024] The function of the diode-connected transistor 52 is to supply additional current to the current source I1 during the overdrive condition. During the overdrive condition, the current source I1 in the exemplary circuit arrangement shoWn by the FIGURE requires a current of 1000\$\times\$10 uA or 10 mA.

In order for this to happen, you need to either use a p-channel JFET instead of n-channel, or you need to reverse the polarity of your input source (I1), so that it can draw current through the diode-connected FET when the overdrive occurs.

Basically, this circuit only works for one polarity of input current. That's okay, because a lot of typical use cases for TIA's (like amplifying photodetector signals) only involve one polarity of input current.

even though the excess current is limited i want the waveform not to distort, kindly point out flaws in the design

This is not possible. A limiting circuit inherently introduces distortion into a signal. Imagine you input a large-amplitude sine wave into a limiting circuit. The output would be closer to a square wave. This is a textbook case of distortion, and is the expected and desired result when you use a limiting circuit.

Possibly you should consider an automatic gain control (AGC) amplifier instead of a limiter.

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  • \$\begingroup\$ thanks a lot it helped me very much, i can accept you answer, but i want to realize it practically so updated the question, as the real problem is how to actually realize the current source. \$\endgroup\$ – kakeh Jun 7 '16 at 3:49
  • \$\begingroup\$ @kakeh, on an IC, probably current mirrors. That's also possible at the pcb level, but for maximum accuracy you might need to make some more complex op-amp current source circuit. \$\endgroup\$ – The Photon Jun 7 '16 at 4:24
  • \$\begingroup\$ Notice you don't really need the two current sources to have any particularly accurately set value, or even to be stable with time/temperature/Vcc. You just need them to be very very close to equal to each other. \$\endgroup\$ – The Photon Jun 7 '16 at 4:25
  • \$\begingroup\$ no, but the patent clearly says the current source value is the limiting value, then if want to limit the current to 10mA then i should have current source value to be 10mA , isn't it ? \$\endgroup\$ – kakeh Jun 7 '16 at 4:58
  • \$\begingroup\$ @kakeh, sure. But if it was sometimes 9.9 mA or 10.1 mA, it wouldn't be a big problem. You normally make the limit value well outside your normal signal levels. You only have the limit circuit to deal with abnormal situations. \$\endgroup\$ – The Photon Jun 7 '16 at 5:19

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