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I've been trying to plan out a new project for a while. It's a wideband antenna anaylyzer for radio applications. I've figured out most of the details, but the most important part - the frequency source - has me stumped.

I'm trying to figure out the best way to cover the frequency range of ~1MHz to ~1GHz, which would cover pretty much all of the communications frequencies in use today.

I was originally planning on using a DDS chip like the AD9910, which is around $40 and about the most I want to spend on a single component. The problem with that chip is that even with a 1G reference clock it still goes downhill pretty quickly after 400MHz. Analog has more options, but price ramps up pretty steep after this chip.

The Si570 series from Silicon Labs was another idea I was tossing around, but the output of the 10M-1.4G chip is LVDS which is not easily converted to a sine wave without a lot of filtering.

A PLL was something I was tossing around, but I haven't done much research into them and it seems that most chip offerings are designed for higher microwave applications.

I know regardless of what I use I'll be including switchable filter banks to cover the entire range. I would love to hear input from some people who have more experience with RF design and see what you guys think I should be using to generate these frequencies. And by all means, feel free to tell me that what I'm doing is a very tall order.

And yes, I'm aware there are commercial options that I could buy instead of building an antenna analyzer myself, but where's the fun in that? This will be used for mostly amateur radio applications, so I'd love to homebrew something together.

UPDATE:

I'm now considering using the AD9910 coupled with a frequency multiplier of some kind to reach the desired range of 1 to 800 MHz. This could be the best option, if I can find a suitable chip for a reasonable price.

Thanks for the help.

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  • \$\begingroup\$ For inspiration you could look at how commercial ones are made at last. \$\endgroup\$ – PlasmaHH Jun 6 '16 at 15:24
  • \$\begingroup\$ Nyquist sampling theorem should tell you that a 1 Gsps DDS isn't going to be able to generate an output above 500 MHz. \$\endgroup\$ – The Photon Jun 6 '16 at 15:36
  • \$\begingroup\$ So, if I understand you correctly, a critical part of this project is a clock source that can be adjusted between 1MHz up to 1GHz? Or do you need a sine wave? \$\endgroup\$ – uint128_t Jun 6 '16 at 15:37
  • \$\begingroup\$ Well ideally a sine wave output would be best, but with suitable filtering a square wave or other clock source could be used. But the end goal is a sine wave for RF applications. \$\endgroup\$ – Patrick Jun 6 '16 at 15:38
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    \$\begingroup\$ It is necessary to output a single frequency at a time to the antenna under analysis. What happens on the board level to get to this single frequency doesn't necessarily matter. \$\endgroup\$ – Patrick Jun 6 '16 at 15:57
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Texas Instruments has a component that can do the majority of your desired RF output range: LMX2571. At around $12, quantity 1, on Digikey, this will successfully implement 10MHz to >1GHz signal synthesis. It also has an internal VCO, so its output range will not be dependent on an external VCO's frequency range.

Along with a high quality, but not necessarily as high-spec as the AD9910 that you suggested, you could probably cover audio (kHz) to 50MHz effectively for HF radios, then cover 30m/10MHz and higher frequencies with the LMX RF synthesizer.

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  • \$\begingroup\$ I think this might be the winner. If this PLL goes down to 10MHz no problem, then I should be fine scaling back the DDS for lower frequencies to the classic AD9850 or something even less feature-rich. No sense paying $40 for 10Mhz. Thanks for finding that chip. I would've never thought to look through TI's offerings. \$\endgroup\$ – Patrick Jun 6 '16 at 20:43
  • \$\begingroup\$ TI indeed has some remarkable offerings. The LMX2571 is "as low as they go" for all of the RF frequency synthesizers there. \$\endgroup\$ – user2943160 Jun 6 '16 at 20:44
  • \$\begingroup\$ Now I just need to learn how to use the thing. I'm not a hardcore programmer by any means, so I'm going to be doing quite a bit of datasheet reading. \$\endgroup\$ – Patrick Jun 6 '16 at 20:55
  • \$\begingroup\$ Yup. It's going to be many pages of reading to figure out even the basic operation. \$\endgroup\$ – user2943160 Jun 6 '16 at 21:35
  • \$\begingroup\$ I was thinking about a new issue this chip brings up: to analyze the antenna properly you need minimal harmonics, IE sine wave. Filtering across this frequency range is going to be near-impossible to do without a large amount of filters for each segment. \$\endgroup\$ – Patrick Jun 7 '16 at 15:05
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You might want to try a combination of a high frequency RF synthesiser, say the ADF4360-7, and your DDS for the low frequency tranche. The RF synth can generate the clock signal for the DDS.

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  • \$\begingroup\$ Interesting idea. Like I said above, I know almost nothing about PLL/VCO synths so I'm going to have to do some reading up on the datasheets. However both of you have similar ideas and I might take that approach. \$\endgroup\$ – Patrick Jun 6 '16 at 19:19
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As usual it's the higher frequencies that will cause the most heartache. Yes DDS is good into the low hundreds of MHz and you can have a nice little low pass filter on the output to keep sinewave quality. As you drop in frequency the sinewave quality improves because more samples are used in the generation of the sine wave. However, don't rule out that some "variable" sinewave purity filtering may be needed all the way down to the low tens of MHz and this will still be a little tricky.

The problem with hundreds of MHz is that to obtain decent waveform purity sine wave voltage controlled oscillator are used and these are limited in their control range to about 2.5:1. This is because they use varactor diodes and they only usually have a maximum capacitance tuning range of about 6:1. It's the square root of the capacitance that controls frequency change hence that is why I mentioned the overall VCO tuning range to be about 2.5:1.

So, using a PLL (or maybe two) create two "locked" oscillators that cover the range 1 GHz down to about 160 MHz. That's how I would approach it.

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  • \$\begingroup\$ For this application, if I use DDS for the lower frequencies there shouldn't need to be much in the way of filtering. AD's specs on spurs and harmonics are pretty impressive when you're in the operating frequency range. I really don't know much about designing PLL's. Got any good resources? If not I'm sure I can find some online. \$\endgroup\$ – Patrick Jun 6 '16 at 19:10

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