The most typical "soft" error in DRAM consists in the loss of charge by the bit capacitor. Capacitors which were not charged to begin with rarely get any charge from the thin air. Charged capacitors lose their charge naturally over time, and this process is accelerated by faulty gate transistors, cosmic rays switching such transistors to conductive state, and dielectric imperfections.
Whenever a charged capacitor represents logical 0 or 1 is defined by the DRAM implementation. First generations of DRAM had the capacitor tied to ground and used to represent logical 1 with a charged capacitor and logical zero by a discharged one, so typical errors manifested in ones turning into zeroes:
simulate this circuit – Schematic created using CircuitLab
Modern DRAM is a bit different, with the capacitor being tied to VCC/2 potential instead of ground:
In modern DRAMs, a voltage of +VCC/2 across the capacitor is required to store a logic one; and a voltage of -VCC/2 across the capacitor is required to store a logic zero.
This make both 1->0 and 0->1 errors equally probable, at least among many DRAM chips. A particular DRAM chip can still have different probabilities for these errors if VCC/2 potential is consistently interpreted as either 0 or 1.
Earlier DRAM implementations used more exotic bit representation schemes (like encoding pair and unpair bits differently), but I can't find any references.