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this is about DDR memory data corruption and not about STUCK address or data lines. If we have a good DDR with no memory stuck issues and we perform lots of writes and reads which type of error is more prominent

  1. 0 getting converted to 1
  2. 1 getting converted to 0

Where can I get such statistics.

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    \$\begingroup\$ Even if there is a bias one way or the other, why does this matter? \$\endgroup\$ – Dave Tweed Jun 7 '16 at 11:23
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    \$\begingroup\$ What if I told you: "Due to solar emitted nano particle waves and the influence on their off-axis spin induced by the earth's magnetic field on the charge stored in DRAM capacitors and the impurities in Silicon protons, a 0 getting converted to a 1 is 0.148 % more likely to happen." How would that change your life from now on ? \$\endgroup\$ – Bimpelrekkie Jun 7 '16 at 11:38
  • \$\begingroup\$ What the two other comments said. Generally, rest assured that in any sensibly designed link, both probabilities should be around the same. Otherwise, it would be mathematically obvious that one can either improve the systems energy consumption without reducing error safety, or improve the systems error security by changing it without making other things worse. In essence, every code will try to lose as little Shannon information on the link, which implies the error probabilites on the link should be made symmetric. \$\endgroup\$ – Marcus Müller Jun 7 '16 at 11:58
  • \$\begingroup\$ Does repeated charging and discharging of capacitors inside DRAM memory degrade the capacitor ? If yes then what effect will that have ? \$\endgroup\$ – arun Jun 7 '16 at 13:15
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    \$\begingroup\$ Thanks @winny. I have floated a mail in memtest. lets see if they collect any statistics \$\endgroup\$ – arun Jun 8 '16 at 11:46
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The most typical "soft" error in DRAM consists in the loss of charge by the bit capacitor. Capacitors which were not charged to begin with rarely get any charge from the thin air. Charged capacitors lose their charge naturally over time, and this process is accelerated by faulty gate transistors, cosmic rays switching such transistors to conductive state, and dielectric imperfections.

Whenever a charged capacitor represents logical 0 or 1 is defined by the DRAM implementation. First generations of DRAM had the capacitor tied to ground and used to represent logical 1 with a charged capacitor and logical zero by a discharged one, so typical errors manifested in ones turning into zeroes:

schematic

simulate this circuit – Schematic created using CircuitLab

Modern DRAM is a bit different, with the capacitor being tied to VCC/2 potential instead of ground:

In modern DRAMs, a voltage of +VCC/2 across the capacitor is required to store a logic one; and a voltage of -VCC/2 across the capacitor is required to store a logic zero.

This make both 1->0 and 0->1 errors equally probable, at least among many DRAM chips. A particular DRAM chip can still have different probabilities for these errors if VCC/2 potential is consistently interpreted as either 0 or 1.

Earlier DRAM implementations used more exotic bit representation schemes (like encoding pair and unpair bits differently), but I can't find any references.

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  • \$\begingroup\$ any idea what is the most common DRAM implementation ? charged capacitor represents 0 or 1 ? \$\endgroup\$ – arun Jun 7 '16 at 14:00
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    \$\begingroup\$ a voltage of +VCC/2 across the capacitor is required to store a logic one; and a voltage of -VCC/2 across the capacitor is required to store a logic zero So this makes 0 -> 1 transition and 1 -> 0 transition equiprobable \$\endgroup\$ – arun Jun 8 '16 at 4:42
  • \$\begingroup\$ @arun Good point, I think you're right. I'll update my answer. \$\endgroup\$ – Dmitry Grigoryev Jun 8 '16 at 5:46

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