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I am doing pulse measurement to solve the self-heating problem.

I control the frequency and duty cycle.

I know that pulse width = duty cycle / (frequency *100).

I want to know what the boundary condition is.

In other words, I want to determine at what point I transition between isothermal and self-heating.

Does 2 % of duty cycle signal cause the 2 % of power dissipation?

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  • \$\begingroup\$ What is the device, and why is self-heating a problem? \$\endgroup\$ Commented Jun 7, 2016 at 23:08
  • \$\begingroup\$ As I increase the gate voltage of nmos, Id- vd curve show me the self heating problem. After saturation point, Id decreases because of self-heating. \$\endgroup\$
    – noah k
    Commented Jun 7, 2016 at 23:15
  • \$\begingroup\$ What specific NMOS devices are you working with? Please post at least the device name, if not also the manufacturer's datasheet. \$\endgroup\$ Commented Jun 7, 2016 at 23:50

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Does 2 % of duty cycle signal cause the 2 % of power dissipation?

If the device isn't affected by the temperature change then a 2% duty cycle will cause 2% of the steady state power dissipation on average. However for the short time that it is turned on the device will be receiving full power, and this will cause a higher peak temperature rise inside it.

How high internal temperature will go depends on the instantaneous power, the time it is applied for, the thermal mass of the active part (the 'junction' in a MOSFET) and the thermal resistances of whatever 'heat-sinking' it has to ambient (substrate, lead frame, wires, packaging, external heat sink, PCB etc.).

If you know all the thermal parameters then you can calculate the temperature rise by analyzing an electronic 'equivalent circuit' where thermal mass is represented by capacitors and thermal resistance by resistors. Thermal power is 'current', and temperature is 'voltage'. The circuit might look like this:-

schematic

simulate this circuit – Schematic created using CircuitLab

40W watts of thermal power (represented by the current generator) is being pumped directly into the junction. Because the junction has low thermal mass (Cj) it will 'charge up' (increase temperature) very rapidly. However it is in close contact with the substrate, which draws heat away (through 'resistor' Rjs) to fill its own thermal 'capacitor'. This continues down the line, with each component initially absorbing heat and then passing it on until finally the heat goes to 'ground' (ambient environment).

At each stage the different capacitances create different thermal time constants, and the resistances cause a temperature rise as the heat flows through them. The junction is small so its temperature rises very quickly - eventually stabilizing when all the heat flows through Rjs to the substrate. But the substrate also soon heats up, raising the junction temperature even higher. The case and heatsink have a similar effect, with each stage causing another 'bump' in junction temperature.

But what does this mean for your duty cycle calculations?

Firstly, you must take into account not just the on/off ratio, but also the pulse time. A duty cycle of 2% with a PWM period of 1 second (20ms 'on' time) might have a quite different effect than the same duty cycle with a period of 1ms (20us 'on' time).

Secondly, you cannot assume that PWM will create a junction temperature proportional to the ratio. The average power might be 2%, but the junction temperature will rise and fall as the power is switched on and off - and you can't tell how much or how fast it is varying by measuring the case temperature.

Bottom line - use the shortest pulse width that still enables you to get accurate measurements, and make the resting time as long as practicable. If you get the same results when the pulse time is increased or resting time reduced (and you are still within the device's safe operating area) then you can use it.

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There's three main sources of heat in a fet that's running in a pulsed/switching configuration: The switching losses, the conduction losses and the gate losses.

The switching losses occur because a fet cannot switch instantaneously between off and on, there is a period where it is somewhere in between the two and acts like a variable resistor (the fet passes through both the saturation and triode regions as the gate voltage ramps up where it can potentially be very lossy). This event happens once at turn on and once at turn off and should take roughly always take the same time assuming the gate drive circuitry behaves the same way at all frequencies. So the switching losses account for a fixed energy loss each cycle.

The gate losses occur because there is some internal gate resistance and because you need a flow of current to change the voltage across a capacitor (the gate capacitance), there will be some fixed energy loss across the gate resistance each switching cycle as the gate is charged and discharged. This also accounts for a fixed energy loss each switching cycle (I2R*t).

The third loss, the conduction loss, is a bit different. The conduction loss happens when the fet is already on (i.e. after the switching transitions have finished) so the losses here have nothing to do with frequency but are instead dependent on the duty cycle as a larger duty cycle means that on average the fet spends more time turned on burning power (\$P = Vds*Ids = Ids^2*Rds\$). (Note I used the term 'power' and not energy as the conduction losses relate to an ongoing effect as opposed to a one-off, a constant power loss which is frequency independent as opposed to a constant energy loss which is not frequency independent). If you don't have a high enough Vgs to turn the fet fully on, then it will spend this time in either the saturation (constant Ids) or triode (constant Rds) regions (which still represent conduction losses) and will behave accordingly.

The point at which the switching (and gate losses, which are often rolled into the switching losses) become greater than the conduction losses will be different for different fets, for different operating temperatures, for different drain voltages, different drain currents, different gate voltages, for different gate charge times (charging/discharging the gate faster reduces the switching losses) and will even be different between batches of the same fets. I know you were hoping for a simple answer, but the reality is that MOSFET losses are very complex and difficult to model, Fairchild makes a good switching loss calculator spreadsheet (which is good but still not perfect) although it's only valid for a synchronous Buck converter configuration. The only times that fet losses are straight forward to calculate is when the fet is in one particular state (off, triode, saturation, fully enhanced etc.), when Tj, Vds, Ids, Vgs are all fixed and the fet is not switching. Anything else gets complicated really fast - the best way to deal with this is to just run empirical tests and see what the results are, just be aware that any changes to your test setup will result in changes in your results.

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  • \$\begingroup\$ This question is likely not about power loss in the FET due to its use as a switching element. Rather, it seems to be about semiconductor parameter analysis and avoiding the impact of self-heating on the device parameters being extracted. \$\endgroup\$ Commented Jun 8, 2016 at 1:22

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