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I am trying to make a ring oscillator inside of a Xilinx's CoolRunner-II CPLD and trying to measure how many ring-oscillator cycle fits inside a low half of external 10MHz clock. Below is simple code i made using 5 inverters.

module Top(
    input clk,
    input trig,
    output TXD
    );

 wire node1;
 wire node2;
 wire node3;
 wire node4;
 wire node5;
 wire node6;
 wire node7;

reg[31:0] counter;
reg[31:0] counterBuf;

assign node1 = ~node7;
assign node2 = ~node1;
assign node3 = ~node2;
assign node4 = ~node3;
assign node5 = ~node4;
assign node6 = ~node5;
assign node7 = ~node6;

always @(posedge node5) begin //use ring counter clock
    //increase counter only during low period of clock
    if(clk==0) counter = counter + 1;
    else begin
        counterBuf = counter;//save counter value for later use
        counter = 0;//restart counter
    end
end

However, I try to read counterBuf, it always reads 0. If i comment out "counter=0;", counterBuf shows some change in value. Is the code wrong in esetting the counter?

How can I implement otherwise using verilog?

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  • \$\begingroup\$ Your code seems quite incomplete. Nothing appears to drive "node5" It may also require no small amount of care to get synthesis tools to create the ring oscillator you desire - and even more so for simulation tools to model it. \$\endgroup\$ Jun 9, 2016 at 8:08
  • \$\begingroup\$ @ChrisStratton I have left out that part of the code by mistake. Now' it's added. \$\endgroup\$
    – Steve
    Jun 9, 2016 at 8:15
  • \$\begingroup\$ Not sure if it makes sense. The verilog compiler will certainly optimize this out, because it doesn't know you actually want all those inverters, with their side effects (added delay). I'm not sure you can do that, at least cetainly not in this way. In bigger devices, you have PLLs or clock generators. Not sure about CoolRunner. \$\endgroup\$
    – dim
    Jun 9, 2016 at 8:21
  • \$\begingroup\$ @Steve : Frequency of operation of ring oscillator is what? \$\endgroup\$ Jun 9, 2016 at 9:26
  • \$\begingroup\$ @PrakashDarji: It seems he can't manage to measure anything relevant. That's the problem. \$\endgroup\$
    – dim
    Jun 9, 2016 at 9:55

1 Answer 1

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Check your compiler logs. You will almost certainly find something saying "Combinational loop removed" - the synthesis tools will not allow this unless you specifically tell it to preserve each as a separate LUT. Have a look at the post-fit netlist and see what the synthesizer is producing.

Oscillators are not good for FPGAs as depending on the length of the chain and propagation delays, you can easily get several hundred MHz if not GHz signals which can burn out the device with excessive switching currents.

Even if it does keep the loop, you will almost certainly get odd behaviour. The oscillator will toggle so fast and with so much jitter that you will violate the setup and hold times of your counter which will result in weird behaviour.

Then if you are comparing it with a clock (which is also not good) of 10MHz, that means the counter is going to get reset for 50ns in every 100. Because this oscillator and the external clock are both asynchronous with no synchronisation, you will end up again violating setup and hold times of the output register and cause it to go metastable 0 - who knows what it will output then.

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