Is it safe to use "weak" signal declarations in VHDL?
There are the signals 'H' 'W' and 'L', that act as logic declarations, but which can be overridden by strong signals like '1' and '0'. I assume these are meant to mimic pulldown or pullup resistors.
I want to have a register that can switch directions, so I used inout for the input and output ports, and 'W' for the input side.
So, for example, when the direction port reads low,
input <= 'W'; output <= input;
and when direction is high,
input <= output; output <= 'W';
that way, when input is 'W', if the port is driven high, with a logical '1' from the external port, that overrides the 'W' and if it's low with a '0' that overrides the 'W'. I did this because otherwise there's a conflict of multiple drivers.
My questions is, is this allowed? Technically the behavioral simulation works out like I want, but I know VHDL being syntactically correct doesn't necessarily mean it would work on an FPGA. Does PL fabric support this?