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In RISC vs CISC, the load/store architecture:

  1. Load memory data into CPU register
  2. Compute
  3. Store result in memory

In CISC, 1,2,3 is wrapped in a single instruction. In RISC 1,2,3 are separate instructions.

I'm reading from Naimi - AVR's and he says:

The problem is there might be a delay in accessing the data from external memory. Then the whole process would be stalled, preventing other instructions from proceeding in the pipeline. In RISC, designers did away with these kinds of instructions.

So if there's bus contention, there's a delay and the process will stall.

But surely it'll stall in RISC as well? So what's the significance of wrapping 1,2,3 in a single instruction (CISC) vs keeping 1,2,3 as independent instructions (RISC-ARM)?

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What you mention is only one of many differences between CISC and RISC.

One way that RISC tries to minimize memory stalls is by having the compiler schedule the memory accesses. With CISC, the compiler has little opportunity to optimize memory accesses, but an advantage of RISC's simpler, single-cycle instructions is that it can rearrange those instructions at compile-time to optimize memory accesses. CISC instructions are too complex for the compiler to know when and where instructions can be rearranged. RISC's advantage partially depends on an optimizing compiler understanding how instruction flow can be manipulated.

There are other attributes of RISC that are meant to offer improvements. One is heavy pipe-lining, another is the potential for faster clock speeds, and a third is instruction and data caches. However, CISC architectures have adopted many of the techniques that were envisioned for RISC, and have tended to keep up with RISC in performance.

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The difference is that you can anticipate the delay, and place unrelated instructions in the slots after the load, which will not be stalled because they are not dependent on the load to complete.

The destination register of the load will have indeterminate value until the load is completed; different architectures have different mechanisms to track outstanding loads -- a possible implementation would mark the destination register as invalid in an early stage, so the next instruction would stall if it tried to read, and reset that flag on completion of the load instruction.

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RISC vs CISC has become more of a theoretical debate since about 1995, when Intel introduced RISC a core in x86, and ARM extended their instruction set with Thumb, stepping away from RISC philosophy of fixed instruction length. None of the modern CPUs are pure RISC or CISC.

Regarding pipeline stalls, it's all about avoiding hazards in the pipeline. Complex instructions will have more hazards, which may be harder or impossible for the compiler to avoid. Simple instructions with few side effects will have less hazards and give more freedom to compiler or CPU to execute them out of order.

In your example, the CISC processor will be busy executing your instruction for as long as reading them memory in step 1 and writing memory in step 3 take. A RISC processor could execute different "compute" instructions in parallel with steps 1 and 3, doubling the performance in an ideal case.

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