In RISC vs CISC, the load/store architecture:
- Load memory data into CPU register
- Store result in memory
In CISC, 1,2,3 is wrapped in a single instruction. In RISC 1,2,3 are separate instructions.
I'm reading from Naimi - AVR's and he says:
The problem is there might be a delay in accessing the data from external memory. Then the whole process would be stalled, preventing other instructions from proceeding in the pipeline. In RISC, designers did away with these kinds of instructions.
So if there's bus contention, there's a delay and the process will stall.
But surely it'll stall in RISC as well? So what's the significance of wrapping 1,2,3 in a single instruction (CISC) vs keeping 1,2,3 as independent instructions (RISC-ARM)?