A Digital board has a Unipolar square clock of 250 MHz. If the clock on the board at all places should have all the harmonic components which have more than 10% of DC value, the board has to be designed of atleast-
A)250 MHz B)750 MHz C)1250 MHz D)2500 MHz
The answer given is 1250 MHz. Can you explain how to solve this problem?
For convenience numerically I'm assuming that the DC voltage of the power rail is 2V. This makes the sq wave clock amplitude 2 Vp-p (assuming a perfect output stage).
The amplitude of the fundamental sinewave of the clock is slightly higher at 2 Vp-p x 4/pi = 2.546 Vp-p or 1.273 Vpeak.
So, the question really becomes what highest frequency harmonic has a peak amplitude that exceeds 0.2 Vpeak (10% of DC rail).
Square wave harmonics are like this (frequency is irrelevant): -
As you can see the fifth harmonic is one-fifth down on the fundamental and in our case it will have an amplitude of 0.2546 Vpeak (still above 0.2 Vpeak). However, the 7th harmonic will have an amplitude of 0.182 Vpeak hence the fifth harmonic is the highest frequency that still has an amplitude greater than 10% of the DC rail.
250 MHz x 5 = 1250 MHz.
