How to latch on 2ns square pulse, if the propagation delay of our fastest gate is greater (let's say 10ns) ?
In other words how to detect pulses shorter that the inertia delay of our fastest gate?
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Your question is not clear. To "latch," you mean to synchronize (like one oscillator latches to another), or latch as in a counter? In either case, gate delay per se, is not a problem, all it does is delay the output. So if you have 10 pulses coming in, you will get 10 pulses out, just delayed by the amount of the gate delay.
For a counter application, the pulse repetition rate is the one that can cause a problem. If the rep. rate is faster than the first flip-flop latch time, then you will miss pulses (you should use the fastest edge triggered flip-flop as your first stage).
For the oscillators case, you use a PLL to keep one oscillator synchronized (latched) to the other.