How to latch on 2ns square pulse, if the propagation delay of our fastest gate is greater (let's say 10ns) ?

In other words how to detect pulses shorter that the inertia delay of our fastest gate?

  • \$\begingroup\$ Have you actually tried this so you know that it doesn't work? \$\endgroup\$
    – pipe
    Commented Jun 16, 2016 at 20:28
  • \$\begingroup\$ Yes I tried. The 2ns pulse will be treated like a glitch (hazard) and simply can't get through the gate. There is not enough time for the pulse to saturate the transistors. \$\endgroup\$ Commented Jun 17, 2016 at 2:43
  • \$\begingroup\$ Is this VLSI stuff? Or are you using physical components? If the former, what other elements can you make (e.g. R, C, diode?). If you can make a fast enough diode to catch the pulse and a high resistance, you can make a simple pulse extender. \$\endgroup\$ Commented Jun 17, 2016 at 3:29
  • \$\begingroup\$ It is CMOS IC design, but I am not working on the IC design itself, but a higher lever of abstraction (Transistor level). Diodes are complex to design using CMOS technology. Using Caps are possible but they consume huge die area. "Pulse extender" is an option, yes, you are right. \$\endgroup\$ Commented Jun 17, 2016 at 3:50
  • 1
    \$\begingroup\$ A diode in series with the signal into an CMOS buffer (which has inherent input capacitance) with a bleed resistor will make a simple pulse extender if you can make a diode fast enough. \$\endgroup\$ Commented Jun 17, 2016 at 4:41

1 Answer 1


Your question is not clear. To "latch," you mean to synchronize (like one oscillator latches to another), or latch as in a counter? In either case, gate delay per se, is not a problem, all it does is delay the output. So if you have 10 pulses coming in, you will get 10 pulses out, just delayed by the amount of the gate delay.
For a counter application, the pulse repetition rate is the one that can cause a problem. If the rep. rate is faster than the first flip-flop latch time, then you will miss pulses (you should use the fastest edge triggered flip-flop as your first stage).

For the oscillators case, you use a PLL to keep one oscillator synchronized (latched) to the other.

  • 1
    \$\begingroup\$ Digital latch, e.g. SR Latch. What you are talking about is transport delay which is not a problem. But what I refereed to in my question is inertia delay, which is indeed a problem. \$\endgroup\$ Commented Jun 17, 2016 at 2:49

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.