I'm interfacing the Nordic nRF52 chip with an FPGA, and sometimes I need MOSI to be at a high impedance state (read "Z" in VHDL). Else the slave won't acknowledge that the data has been transferred completely (see here for the SPI Slave I'm using).

How should I do that properly?

  • \$\begingroup\$ You won't be able to "read" a Z in VHDL when synthesized. FPGAs have no understanding of "Z", the input signal will be either high or low. I think you are missing the purpose of the slave select pin. \$\endgroup\$ – Tom Carpenter Jun 15 '16 at 17:12
  • \$\begingroup\$ Right, the slave select pin changes state depending on data being transferred or not. I see why my question is stupid now. I can't reproduce the signals I'm having in simulation so I'm trying to find a cause here, this is obviously not it. My problem is (see link above) the trdy bit doesn't go (or stay? Maybe it goes low/high in a clock) when the last bit is sent to the master, despite receiving it correctly on the nRF52. So I'm confused :( Thanks for pointing out my mistake, still \$\endgroup\$ – Fluffy Jun 15 '16 at 18:28

MOSI (Master Out Slave In) is an input on the slave, so it is always high impedance. The slave won't be able to tell if the MOSI line is high impedance at the master, but then it doesn't need to. If the slave is selected (SS low) then it expects to see 1's and 0's on MOSI. If it is deselected then it doesn't care.

The reason for having high impedance on MISO (Master In Slave Out) in the slave is so you can have several slaves on the same SPI bus. When SS (Slave Select) is high the slave makes its MISO output high impedance, so it won't collide with another slave which might be selected.

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