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FINAL UPDATE: Understand a previously mysterious power MOSFET switching waveform wiggle! @Mario uncovered the root cause here below, distinctive to so-called VDMOS devices, typical of many power MOSFETs like the IRF2805.


UPDATE: Found a clue! :)

@PeterSmith mentions an excellent resource on understanding gate charge specs in MOSFET datasheets in one of the comments below.

On page 6, at the end of the second paragraph, there's a passing reference to the idea that \$C_{GD}\$ becomes constant (stops varying as a function of \$V_{DS}\$) when \$v_{GD}\$ > 0. It doesn't mention the mechanism, but it got me thinking about what might be happening with \$v_{GD}\$ at the knee:

enter image description here

And son-of-a-gun, it turns out to be right where \$v_{GD}\$ rises above 0V.

So if anyone understands what that driving mechanism is, I think that would be the right answer :)


I'm making a close study of MOSFET switching characteristics as part of my study of switching converters.

I've set up a very simple circuit like so:

enter image description here

Which produces this MOSFET turn-on waveform on simulation:

enter image description here

A knee appears in the drain voltage drop about 20% into the Miller plateau.

I built the circuit up:

enter image description here

And the scope confirms the simulation quite well:

enter image description here

I believe I understand the "pre-shoot" bump (\$C_{gd}\$ charging current running "backward" through the load resistor), but am mystified as to how to account for the knee in the drain voltage drop.

Can someone more experienced with MOSFETs help me understand?

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    \$\begingroup\$ Ok, than yes, it happens when you charge the capacitance between gate and drain. I that time the Ids is constant, nice feature for certain applications \$\endgroup\$ – Gregory Kornblum Jun 18 '16 at 6:08
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    \$\begingroup\$ Looks like Miller Effect from Cgd? If you add a 100pF cap from gate to drain, does that exacerbate it? \$\endgroup\$ – Krunal Desai Jun 18 '16 at 6:33
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    \$\begingroup\$ Don't know the answer, but this Vishay Siliconix application note titled "Power MOSFET Basics: Understanding Gate Charge and Using it to Assess Switching Performance" might be helpful: vishay.com/docs/73217/73217.pdf \$\endgroup\$ – Jim Fischer Jun 18 '16 at 7:00
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    \$\begingroup\$ The real gate charge (Qg) for switching analysis has a sensitivity to Gate resistance. In addition, Cgd varies as a function of Vds. See microsemi.com/document-portal/doc_view/… \$\endgroup\$ – Peter Smith Jun 18 '16 at 12:34
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    \$\begingroup\$ @scanny as a note, it is perfectly valid for you to answer your own question ... besides what some other comments may suggest, driving the gate with a resistor does illuminate what is happening. I suggest you look at what happens in the channel, before formation, and after and ask yourself where does the capacitance arise from. Then answer your own question. \$\endgroup\$ – placeholder Jun 18 '16 at 20:08
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The slope of the drain voltage depends on the gate-drain capacitance Cgd. In case of the falling edge the transistor has to discharge Cgd. In addition to the load current for the resistor it also has to sink the current that flows through Cgd.

It is important to keep in mind that Cgd is not a simple capacitor but a nonlinear capacitance that depends on the operating point. In saturation there is no channel at the drain side of transistor and Cgd is due to the overlap capacitance between gate and drain. In the linear region the channel extends to the drain side and Cgd is bigger because now the large gate to channel capacitance is present between gate and drain.

As the transistor transitions between saturation and linear region the value of Cgd changes and therefore also the slope of the drain voltage.

Using LTspice Cgd can be inspected by using the "DC operating point" simulation. The results can be viewed by using "View/Spice Error Log".

For a Vgs of 3.92V Cgd is about 1.3npF because Vds is high.

   Name:          m1
Model:      irf2805s
Id:          1.70e-02
Vgs:         3.92e+00
Vds:         6.60e+00
Vth:         3.90e+00
Gm:          1.70e+00
Gds:         0.00e+00
Cgs:         6.00e-09
Cgd:         1.29e-09
Cbody:       1.16e-09

For a Vgs of 4V Cgd is much larger with around 6.5nF because of the lower Vds.

Name:          m1
Model:      irf2805s
Id:          5.00e-02
Vgs:         4.00e+00
Vds:         6.16e-03
Vth:         3.90e+00
Gm:          5.15e-01
Gds:         7.98e+00
Cgs:         6.00e-09
Cgd:         6.52e-09
Cbody:       3.19e-09

The variation of Cgd (labeled Crss) for different biasing can be seen in the plot below taken from the datasheet. enter image description here

The IRF2805 is a VDMOS transistor that shows a different behavior for Cgd. From the internet:

The discrete vertical double diffused MOSFET transistor(VDMOS) popularly used in board level switch mode power supplies has behavior that is qualitatively different than the above monolithic MOSFET models. In particular, (i) the body diode of a VDMOS transistor is connected differently to the external terminals than the substrate diode of a monolithic MOSFET and (ii) the gate-drain capacitance(Cgd) non-linearity cannot be modeled with the simple graded capacitances of monolithic MOSFET models. In a VDMOS transistor, Cgd abruptly changes about zero gate-drain voltage(Vgd). When Vgd is negative, Cgd is physically based a capacitor with the gate as one electrode and the drain on the back of the die as the other electrode. This capacitance is fairly low due to the thickness of the non-conducting die. But when Vgd is positive, the die is conducting and Cgd is physically based on a capacitor with the thickness of the gate oxide. Traditionally, elaborate subcircuits have been used to duplicate the behavior of a power MOSFET. A new intrinsic spice device was written that encapsulates this behavior in the interest of compute speed, reliability of convergence, and simplicity of writing models. The DC model is the same as a level 1 monolithic MOSFET except that the length and width default to one so that transconductance can be directly specified without scaling. The AC model is as follows. The gate-source capacitance is taken as constant. This was empirically found to be a good approximation for power MOSFETS if the gate-source voltage is not driven negative. The gate-drain capacitance follows the following empirically found form:

enter image description here

For positive Vgd, Cgd varies as the hyperbolic tangent of Vgd. For negative Vdg, Cgd varies as the arc tangent of Vgd. The model parameters a, Cgdmax, and Cgdmax parameterize the gate drain capacitance. The source-drain capacitance is supplied by the graded capacitance of a body diode connected across the source drain electrodes, outside of the source and drain resistances.

In the model file the following values can be found

Cgdmax=6.52n Cgdmin=.45n
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  • \$\begingroup\$ So Mario, your contention is that this knee represents the transition from saturation to linear/triode operation of the MOSFET? I think you're on the right track, but I would expect that transition to occur at a much lower \$V_D\$, on the order of 0.5V or so, where \$V_D\$ = \$V_G\$ - \$V_{Threshold}\$. I think your insight of the drain-end of the channel changing shape at \$V_{GD}\$ > 0 would account for the change in capacitance. Note the two points in your simulation have \$V_{ds}\$ different by 6.5V or so. That doesn't localize the change to speak of :) \$\endgroup\$ – scanny Jun 19 '16 at 1:10
  • \$\begingroup\$ @scanny - The change of Cgd happens over a wider range, I was just too lazy to make an additional simulation in order to find the precise value of Vgs required for a certain Vds. If you do it on your own you will see that Cgd already starts to increase at a Vds of about 5V. \$\endgroup\$ – Mario Jun 19 '16 at 5:19
  • \$\begingroup\$ I added an answer below with a reference I finally found after searching and searching. I studied the MOSFET section in Semiconductor Device Modeling with SPICE; Massobrio, but couldn't find any direct reference or parameter for this. But SPICE must know of course because the simulation tracks the scope trace so well. I'd love to hear what you think about the \$V_{GD}=0\$ inflection in the curve in my answer. It doesn't seem to be reflected in the chart you added, but that one doesn't take changes in \$V_{GS}\$ into account it looks like. \$\endgroup\$ – scanny Jun 19 '16 at 5:48
  • \$\begingroup\$ @scanny - I've added an update with a quote from a reference that shows how Cgd is modelled in case of the used VDMOS transistor. \$\endgroup\$ – Mario Jun 19 '16 at 7:01
  • \$\begingroup\$ Sweet! This explains it! Thanks Mario! :) Where did you find the reference? \$\endgroup\$ – scanny Jun 19 '16 at 7:06
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UPDATE: Mario got the right answer above, so leaving this one just for historical interest. This behavior looks to have everything to do with it being a VDMOS (as are many power MOSFETs I gather), which might explain why many of the general MOSFET resources (that tend to focus on monolithic MOSFETs) didn't mention this phenomenon.


Ok, just as I was about to give up on understanding this, the interwebs have granted me a morsel:

enter image description here

This is from IXYS Application Note AN-401, page 3.

There is no explanation of the device physics behind this, but I'm satisfied enough with this for now. This curve would well account for the inflection I'm seeing.

My attempts to explain it to myself with the dynamics of the channel inversion layer have ended in puzzlement. I see no clear inflection point in what I understand it to look like as when \$V_{GS}\$ = \$V_{DS}\$. (These are my best inferences, not something official I read somewhere.) Note that I used \$V_{GD}\$ here (\$V_{GS} - V_{DS}\$), somewhat unconventionally, knowing that \$V_{GD}=0\$ was what I was looking for :)

enter image description here

If anyone has a reference or knows the physics well enough to explain the curve above I'd be very grateful. I'll give the right answer cookie to anyone who can :)

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I have a question: why should the slope be linear?

In fact, during 150 ns of Miller plateau, MOSFET channel resistance drops from almost infinity to a very small value. Even it drops linearly, the output voltage of divider formed by R=100 Ohms and R DS of MOSFET is not linear.

And there is non-linear dependence of R DS on the gate charge; you cannot find it in datasheets, but we know it is non-linear.

Therefore this behavior is natural.

To my mind, you have really nice test set-up, however, it is not good to drive power MOSFET from 50 Ohms source in real power circuit.

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