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How would someone test Vih, Vil of an input pin (Or VoH, VoL of output pin) of a SoC. With an inverter, you could easily see the results but with a microcontroller/SoC, it seems difficult without the device being used in a circuit.

https://www.arrow.com/en/products/am79c874vd/amd#page-2 For Example

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Picking any input pin on the device, how would I test ViH, ViL?

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  • \$\begingroup\$ Why do you want to test it in the first place? \$\endgroup\$ – Eugene Sh. Jun 20 '16 at 17:33
  • \$\begingroup\$ You should your question more clear \$\endgroup\$ – Nazar Jun 20 '16 at 17:36
  • \$\begingroup\$ An assignment, the datasheet isn't for the part I'm working on. \$\endgroup\$ – hybridchem Jun 20 '16 at 17:36
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You fundamentally misunderstand the data-sheet.

These numbers are guaranteed Max/Min values and you use them as part of your design. If you are driving into the SOC then you must make those levels, if you are receiving the signal then you must be able to handle the at the very Most/Least those levels.

If these values are being exceeded the device won't make it out of the foundry.

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  • \$\begingroup\$ So to test it, I would need to use it in a design. \$\endgroup\$ – hybridchem Jun 20 '16 at 17:39
  • \$\begingroup\$ Well, if by "testing" we mean "verify the spec", it might make sense.. \$\endgroup\$ – Eugene Sh. Jun 20 '16 at 17:40
  • \$\begingroup\$ Yes, Verify the spec. \$\endgroup\$ – hybridchem Jun 20 '16 at 17:42
  • \$\begingroup\$ In this case you make a setup providing the voltage just a bit higher than Vih or a bit lower than Vil, and run a zillion of tests where you check the output is as expected. Then you make a nice table where calculating the statistics and add it to your report. For Vox it's just a measurment over the output voltage in a different conditions. \$\endgroup\$ – Eugene Sh. Jun 20 '16 at 17:45
  • \$\begingroup\$ This is where I get confused, I provide the voltage to the pin, but what output am I checking. \$\endgroup\$ – hybridchem Jun 20 '16 at 17:47
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If by testing you mean verifying that the device is within specifications, you would do it as follows:

  1. Generate test signals (e.g. pseudo random sequences) that fall inside the specified range only by a very small margin. You should use the highest and lowest rise/fall times you expect in your system as test cases. You will have to carefully check that these signals really have the right values at the device pins, otherwise you will only check your PCB layout/setup.
  2. Either use JTAG or use a program on your SoC to verify that the correct levels / patterns are received by comparing to your original sequence. JTAG will only work for rather slow patterns, whereas a custom program will need more work to implement if you are testing many different devices.
  3. Generate test patterns similar to 1. with your device and check that you receive the correct levels within the specified boundaries. Again, pay close attention to your layout/setup to make sure that it is really the device you are testing. You will also need very good power integrity, especially when testing several pins at once. Otherwise your power supply / decoupling will be the source of your errors and not the device itself.

There is automated test equipment available to help you with this task, if you can afford it. You will also need some good lab equipment and will have to closely follow all requirements of the datasheet/appnotes concerning PCB layout.

It might also be a good idea to perform these tasks on a demo board (if available), since this way you will more likely receive helpful feedback from the manufacturer in case you see device failures. They will either be able to reproduce your issue or (more likely) point out the reason why your test does not correspond to the datasheet values.

As you can see, with a SoC you most likely need a PCB to perform these tests. There are little alternatives to that, as most other solutions (bed of nails etc.) might show very different behavior at higher frequencies compared to a properly layouted PCB. A demo board can help and is available for most devices.

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  • \$\begingroup\$ Presumably by "inside the spec" you mean more negative than VIL and more positive than VIH. (And you do not mean "within the range VIL to VIH".) \$\endgroup\$ – gwideman Apr 9 '18 at 1:26
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If you are not a vendor/manufacturer of the IC in question, testing ViH/ViL is nearly impossible unless its complexity is low as an inverter or other simple logic gate.

If you are a vendor/designer of the IC, the IC must have built-in means for testability of these parameters. It is called DFT, "Design For Test". It is the vendor job to characterize their IC to meet the advertised ViH/ViL specifications.

Essentially the DFT features of a IC make it possible to relay the state of every Input pin either into a specially dedicated common output (just like a simple inverter does), or there are dedicated built-in test registers that are accessible via debug chains as JTAG that latch the outcome of GPIO state. These tools are usually not disclosed to public, so a customer can't use them.

To ensure compliance with their own specifications, a manufacturer will run these tests under different chip temperatures, supply voltages, and over various grades of silicon material, which are called "corners" [of validation space]. This is usually done on a very expensive Automatic Test Equipment (ATE machines that cost millions of US$) using "load boards" specifically designed for each particular IC. A massive statistics is gathered and guardbands are added to ensure that the parameter never fails the stated levels.

As result, there is not much sense for a user to re-validate all this massive work, unless you have some problem with signals not getting through. In this case it is the best to get into contact with the vendor of IC for fastest resolution of the issue.

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