Half Bridge with dual powre supply and two N-channel Mosfets?

Question

I wanted to ask (can't find a straight answer) if it is possible to make a half bridge with two N-channel MOSFETs (I have the solution with one nmos and one pmos, but I'd like two nmos).

For the botton Nmos I have a gate driver that is referenced to Ground and V-, and is active low. I'm not sure how it would be with the top nmos.

any help would be appreciated. Thanks you very much.

edit: to answer a couple of questions, this is more or less the system. Ignore values of the load. This is just to show how is the set up. The FPGA gives 2.5/0 V signals (one to turn on a MOSFET and one to turn off the MOSFET). Each driver receives those two signals and it is composed of a BJT stage to bump up the signals and an other BJT stage to drive the mosfets. I cannot show my driver circuits, but the bottom driver is supplyed by +2.5v (this would be the reference) and -24V. I'm just not 100% sure how to make the driver for the top MOSFET, for my current circuit with a top PMOS the gate driver is between +24V and GND

Load to the Half bridge is a LP LC filter and a phase of a motor

Answer 1

There is a large number of drivers available that can be used to drive two NMOS transistors. One example would be the IR2011 from Infineon (formerly International Rectifier).

They use a capacitor to boost the gate voltage of the high-side NMOS.

From the datasheet of the IR2011:

Answer 2

Another way of asking the question is whether N channel MOSFETs can be used in both high and low side switching configuration. Yes, they can.

However, there will be some drawbacks using N channel for the high side switch:

1. The gate voltage needs to be 10 V (typically) or so above the top rail voltage to turn on the FET. Since you probably don't have power at that voltage handy, it has to be made somehow.

   There are "high side" FET drivers that include a charge pump for just this reason. The charge pump is often run from the switching pulses, so this kind of FET driver requires regular edges to keep the gate supply fed.

2. The gate voltage must slew the entire switching voltage plus the gate drive level. For example, if the switching voltage is from 0 to 30 V and the gate requires 12 V for the FET to be fully on, then the gate driver must slew 42 V between off and on.

   This puts a very high slew rate requirement on the gate driver for fast switching. It also increases the nodes in the circuit with high dV/dt on them, which presents more opportunity for noise coupling to elsewhere.