0
\$\begingroup\$

I'm trying to write a loop for two binary values that repeat periodically at a specific amount of time that goes indefinitely or until a certain condition is met.

Here is what I have wrote (below), but the error states that I should be using the 'wait' statement with 'until' but when I use that then it says that the Boolean expression is used incorrectly.

This leads me to believe I'm using the loop wrong or doing something else wrong that I can't figure out.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity moove is 
    port (clk : in std_logic;
        rst : in std_logic;
        count : out unsigned (7 downto 0));
end entity;

architecture moving of moove is
    constant period : time := 19.5 ms;
    constant cycles : integer := 120000; 
begin
    forwrd: process (clk)
    begin
        if rising_edge(clk) then 
            if rst = '1' then
                count <= "00000000";
            elsif rst = '0' then
                for i in 1 to cycles loop
                    count <= "01100100";
                    wait for period;
                    count <= "10010110";
                    wait for period;
                end loop;
            end if;
        end if;
    end process;
end architecture;
\$\endgroup\$
  • 1
    \$\begingroup\$ Are you trying to simulate this code or synthesize it? wait for ... statements are not synthesizable. \$\endgroup\$ – Dave Tweed Jun 21 '16 at 11:11
  • \$\begingroup\$ First, simulate and then synthesize \$\endgroup\$ – Serge Jun 21 '16 at 11:17
  • \$\begingroup\$ Would you have any suggestions to a better approach? \$\endgroup\$ – Serge Jun 21 '16 at 11:19
  • \$\begingroup\$ If you will synthesize it you need to use a separate timer for the period of the signal instead of wait \$\endgroup\$ – Claudio Avi Chami Jun 21 '16 at 11:30
  • 1
    \$\begingroup\$ Do you mean a counter, that will count to a specific value (time) and then i would load my binary value to the signal? \$\endgroup\$ – Serge Jun 21 '16 at 11:37
1
\$\begingroup\$

Here is the working version. I'm using 100kHz clock.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;


entity moove is 
port (clk : in std_logic;
        rst : in std_logic;
        count : out unsigned (7 downto 0));
end entity;

architecture moving of moove is
    signal Cnt: std_logic_vector(11 downto 0);
begin
forwrd: process (clk)
    begin
    if Rst = '1' then 
        Cnt <= (others => '0');
            elsif (rising_edge(Clk))then
            Cnt <= Cnt +1;  
            if (Cnt = "011111010000") then--20ms(2000 clock cycles)
            count <= "10010110";--1.5ms
            elsif (Cnt = "111110100001") then
            Cnt <= "000000000000";
            count <= "01100100";--1ms

end if;
end if;
end process;
end architecture;
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.