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Looking at page 18 of the JEDEC spec on LPDDR2

LPDDR2-S2 also uses a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR2-S2 effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal SDRAM core and two corresponding n-bit wide, one-half- clock-cycle data transfers at the I/O pins.

LPDDR2-S4 and LPDDR2-N also use a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR2-S4 and LPDDR2-N effectively consists of a single 4n-bit wide, one clock cycle data transfer at the internal SDRAM/NVM core and four corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

I am trying to figure out the difference between S2 and S4. Does this mean with a 266MHz clock from the processor, S2 is only capable of transferring 533Mbps while S4 can transfer 1066Mbps at that same frequency?

EDIT: I also found this on the wiki page about prefetch buffers.

The prefetch buffer depth can also be thought of as the ratio between the core memory frequency and the IO frequency. In an 8n prefetch architecture (such as DDR3), the IOs will operate 8 times faster than the memory core (each memory access results in a burst of 8 datawords on the IOs). Thus a 200 MHz memory core is combined with IOs that each operate eight times faster (1600 megabits per second). If the memory has 16 IOs, the total read bandwidth would be 200 MHz x 8 datawords/access x 16 IOs = 25.6 gigabits per second (Gbit/s), or 3.2 gigabytes per second (GB/s). Modules with multiple DRAM chips can provide correspondingly higher bandwidth.

Each generation of SDRAM has a different prefetch buffer size:

DDR SDRAM's prefetch buffer size is 2n (two datawords per memory access) DDR2 SDRAM's prefetch buffer size is 4n (four datawords per memory access)

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  • \$\begingroup\$ Please quote the relevant sections and explain your conclusions. I'm not sure how these details of DDR2 work. \$\endgroup\$ – user2943160 Jun 22 '16 at 2:36
  • \$\begingroup\$ @user2943160 I've added in the sections, sorry I should have made it more clear. \$\endgroup\$ – jack sexton Jun 22 '16 at 2:40
  • \$\begingroup\$ Looks like S4 and S2 define different numbers of physical pins, then? \$\endgroup\$ – user2943160 Jun 22 '16 at 2:43
  • \$\begingroup\$ @user2943160 I don't think so the bus size is standard. 'All LPDDR2 devices use a double data rate archiecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information.' \$\endgroup\$ – jack sexton Jun 22 '16 at 2:51
  • \$\begingroup\$ Essentially, it looks as if the burst size is doubled on -S4 compared to -S2. That will give higher performance at a given clock rate (in most cases) but it will not be doubled. \$\endgroup\$ – Peter Smith Dec 6 '16 at 12:40
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The difference is S2 is the speed (in terms of bandwidth/IO throughput) of LPDDR1, and S4 is the speed you'd expect LPDDR2 SDRAM to be.

This might seem strange, but let me explain through a brief bit of standards history:

LPDDR1 is essentially just DDR1 but at 1.8V instead of 2.5V. It is otherwise the same as what desktops used to use.

The LPDDR2 is not merely incremental performance increase like you're probably used to on desktops, but a much more radical departure from DDR1 and DDR2 RAM in favor of mobile and low power features. It is not at all compatible with DDR1 or DDR2, and honestly ought to have a less-similar name to convey this, in my opinion anyway.

One of the features of LPDDR2 is support different speeds (hence the 'S' before the number) of RAM. LPDDR2-S2 is LPDDR1 memory (in terms of IO throughput) with the extra power saving features and other niceties of LPDDR2. So yes, S2 is going to give you LPDDR1 speeds only, despite being called LPDDR2. This is a good thing however, as in applications with modest throughput requirements, you can take advantage of the lower power and cost of LPDDR1, but also all the improvements and further optimization of power consumption of LPDDR2. If there was not S2 RAM, then the only option would be to use LPDDR1. Also, because of the smaller prefetch buffer size (which I will explain further down), S2 is also lower latency at a fixed clock compared to S4.

S4 ram has twice the throughput of S2 RAM, and has the speed improvement/difference you'd expect to see moving from LPDDR1 to LPDDR2, as well as the increased latency.

Summary: Unlike DDR1 vs DDR2 memory, which was mostly just a performance improvement, LPDDR1 vs LPDDR2 improved performance as well as adding significant power saving features. Slower RAM uses less power, but slower ram using a more recent standard with further improvements to power consumption uses the least. That is what S2 is - the slower LPDDR1 memory but with LPDDR2 power saving improvements.

OK, let's get technical

I superficially answered your question, but here is a much more technical answer as well!

First, I'm going to discuss what DDR memory even is.

SDRAM is arranged in rows of words (which are usually the same length as the width of the bus, so if the bus was 32-bit, a word would be 32-bits long). The row will have lots of words, 2048 would be a normal number today. Each of these 2048 words has a location in the row, which is called a column. Nothing exciting yet - this should be familiar and straight forward so far.

There is an asymmetry in the time it takes to access things in SDRAM, however. It takes the longest of any operation to move to a particular row. Once you are at that row, reading a word from a column in that row is trivially quick. The costly thing is changing rows, but you can read a lot of stuff very quickly if its all on the same row.

Enter prefetching. Most of the time (not always, but definitely the majority), a CPU is going to want words directly adjacent to a word it requests, as well. With SDRAM, the CPU had to ask for each one, and that meant one clock cycle per word.

DDR ram prefetches an additional word, the adjacent word directly after the one the CPU requests. Both are loaded into a prefetch buffer, and are 'burst' out of the IO pins on the rising and falling clock edge. Now, the CPU only asked for the first word, and it may not need or care about the second word, so there is a big assumption here. However, it is so often the case that the CPU does in fact want that second word as well, that DDR memory has indeed yielded large increases in memory performance for computers.

Anyway, this is why the MT/s is double that of the clock. This is what the S2 is referring to - it is using a 2n prefetch, meaning it prefetches 2 words per column request.

DDR2 memory internally doubles the IO clock, yielding 4 edge changes per external bus clock cycle, and uses this to implement an otherwise identical prefetch system as DDR1, only it prefetches 4 words (since it has 4 edge changes to clock them out to the bus on) instead of 2. This is what 4n prefetch refers to, and likewise what the 'S4' suffix in LPDDR2-S4 ram is referring to.

So, at the fundamental technical level, S2 LPDDR2 memory is only going to achieve double the IO clock, just as if it were LPDDR1 memory. In terms of the bus IO, it is LPDDR1 memory, but interfaced like faster LPDDR2-S4 memory. Yeah, the throughput is not so good, but you get lower power, cost, and latency in return. Like most things, it's a trade off. Let your application dictate the one you choose as they both have their uses.

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