I want to generate a 15MHz clock from a 60 MHz clock. The 60 MHz clock has a duty cycle of 50%. The output clock of 15 MHz must have 25% duty cycle. How the following code needs to be modified to vary duty cycle?
entity clkgen is Port ( clk_in : in STD_LOGIC; reset : in STD_LOGIC; clk_out : out STD_LOGIC ); end clkgen; architecture Behavioral of clkgen is signal temp: STD_LOGIC; signal count : integer range 0 to 1 := 0; begin Clock_out : process (reset, clk_in) begin if (reset = '1') then temp <= '0'; count <= 0; elsif rising_edge(clk_in) then if (count = 1) then temp <= NOT(temp); count <= 0; else count <= count + 1; end if; end if; end process; clk_out <= temp; end Behavioral;
@Dave this is what i got. Clk_out is not changing it's value