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I want to generate a 15MHz clock from a 60 MHz clock. The 60 MHz clock has a duty cycle of 50%. The output clock of 15 MHz must have 25% duty cycle. How the following code needs to be modified to vary duty cycle?

entity clkgen is
    Port (
        clk_in  :  in  STD_LOGIC;
        reset   :  in  STD_LOGIC;
        clk_out :  out STD_LOGIC   
    );
end clkgen;

architecture Behavioral of clkgen is
    signal temp: STD_LOGIC;


     signal count : integer range 0 to 1 := 0;


begin
    Clock_out : process (reset, clk_in) begin
        if (reset = '1') then
            temp <= '0';
            count <= 0;
        elsif rising_edge(clk_in) then
            if (count = 1) then
                temp <= NOT(temp);
                count <= 0;
            else
                count <= count + 1;
            end if;
        end if;
    end process;

    clk_out <= temp;     

end Behavioral;

update:

@Dave this is what i got. Clk_out is not changing it's value

enter image description here

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  • 1
    \$\begingroup\$ So now you are toggling the output every two clock cycles on each level. You need to have the high level to last one clock cycle, but the low level to last 3 cycles. Now implement it. \$\endgroup\$ – Eugene Sh. Jun 22 '16 at 20:36
  • \$\begingroup\$ "The output clock of 15 MHz must have 25% duty cycle" Why? \$\endgroup\$ – Bruce Abbott Jun 23 '16 at 21:29
  • \$\begingroup\$ That's the requirement. \$\endgroup\$ – user114750 Jun 24 '16 at 13:06
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The simplest thing is to have count counting the full period of the output clock, and then you can assert temp for any fraction of that period, like this:

entity clkgen is
    Port (
        clk_in  :  in  STD_LOGIC;
        reset   :  in  STD_LOGIC;
        clk_out :  out STD_LOGIC   
    );
end clkgen;

architecture Behavioral of clkgen is
    signal temp: STD_LOGIC;
    signal count : integer range 0 to 3 := 0;

begin
    Clock_out : process (reset, clk_in) begin
        if (reset = '1') then
            count <= 0;
        elsif rising_edge(clk_in) then
            temp <= '1' when (count < 1) else '0';
            count <= count + 1;
        end if;
    end process;

    clk_out <= temp;     

end Behavioral;
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  • \$\begingroup\$ "when else " is giving the following error "This construct is only supported in VHDL 1076-2008" \$\endgroup\$ – user114750 Jun 23 '16 at 18:25
  • \$\begingroup\$ If you can't upgrade, you'll have to change it to if count<1 then temp <= '1' else temp <= '0' end if; \$\endgroup\$ – Dave Tweed Jun 23 '16 at 18:52
  • \$\begingroup\$ i simulated the code. it is not generating the 15mhz clock with 25% dc. \$\endgroup\$ – user114750 Jun 23 '16 at 20:10
  • \$\begingroup\$ Well, what IS it doing? Show us some waveforms: clk_in, reset, count and temp. This really shouldn't be hard to debug. \$\endgroup\$ – Dave Tweed Jun 23 '16 at 20:17
  • \$\begingroup\$ If the simulator isn't respecting the range declaration on count, it might be necessary to change the count <= count + 1 statement to if count<3 then count <= count + 1 else count <= 0 end if; I'm relying on the implicit roll-over of a 2-bit counter. \$\endgroup\$ – Dave Tweed Jun 23 '16 at 20:22
1
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Short answer: use the PLL.

Long answer: You need to be careful when routing clocks. Clocks need to be monotonous and need to satisfy the timing requirements. You did not specify whether you are targeting an FPGA or an ASIC. Your synthesis tools are likely to route your signal as a data signal, causing timing violations.

If you do not want to use a PLL, the correct way to implement this is an enable signal. You have a counter that counts up and the enable signal goes high when the counter is about to reset. If you want 25% duty cycle you'll need to use higher frequency and an FSM.

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  • \$\begingroup\$ There's no reason to assume that the synthesis tools will treat the clk_out signal as data, unless they're very old or primitive. If the signal is used as a clock, modern tools will generally treat it as a clock. Another point: When a clock has special duty cycle requirements, that's a clue that it isn't meant to be used on-chip, but rather driven off-chip to some other device. In which case, it is a signal as far as the synthesis tools are concerned, and the usual methods for constraining its timing relative to other I/O apply. \$\endgroup\$ – Dave Tweed Jun 22 '16 at 22:36
  • \$\begingroup\$ Well, my experience is the exact opposite. They may treat it as a clock, but will put logic on the clock line that causes glitches. Also, the OP didn't specify whether this is for an FPGA or ASIC. FPGAs have fixed clock networks that cannot be changed once the device is manufactured. Anyway, it is good practice to use PLLs, as they are designed for this exact purpose, especially when variable duty cycles are required. I take the view that you should never put logic on the clock line. \$\endgroup\$ – user110971 Jun 22 '16 at 22:41
  • \$\begingroup\$ This doesn't answer the question. The question is about a counter for a 25% duty cycle division application. The quality or appropriateness of using this logic-generated signal as a clock is not of concern for an answer. \$\endgroup\$ – user2943160 Jun 22 '16 at 23:23
  • \$\begingroup\$ Well, I just shared my experience about clock division. My last paragraph explains the methodology of using a counter. To be more explicit you simply use a counter that counts from 0 to 3 and use the reset output of the counter, which is high when the counter is about to reset and will give your 25% duty cycle. We need more information from the OP to determine the constraints of the problem. \$\endgroup\$ – user110971 Jun 22 '16 at 23:41
  • \$\begingroup\$ //If you want 25% duty cycle you'll need to use higher frequency and an FSM.// I am targeting an FPGA. Given an input clock of 60 MHz generate a 15MHz clock with 25% duty-cycle without using PLL ---is the question. \$\endgroup\$ – user114750 Jun 23 '16 at 13:31

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