I am modeling Digital Circuits using ICs in a software. I have worked with flip flops and counters, but I don't remember it well. How do I model undefined or initial value of flip flop (SR or JK etc.)? I have three options

  1. '0' state for all uninitialized nodes
  2. assign random value '0' or '1' to the new node
  3. generate error message, & ask user to clear or preset the flip flop

Also consider a JK flip flop, if the user input is '0' & '0', the output is 'Q' & 'Q bar'. What value do I assign in this case? '0' & '1'? This is the initial case, i.e the circuit has been made & the console just powered up.

Please share your experience.


In some types of simulation, the more states the merrier. If you are doing only single-clock synchronous logic, I would suggest three states (high/low/undefined), but expand out the JK flip flop's logic so as to include the full computation of the next value. For example, if one has a circuit in which both J and K inputs are tied to the AND of the output and a RESET signal, one should apply output := (J & !output) | (!K & output), so that the former term will cancel out, leaving output := !RESET & output, whose value would be well-defined if reset is high, even if output is undefined.

If you are trying to do a continuous-time simulation, many more states become necessary, including 'rising', 'falling', 'stable unknown', 'unstable unknown', etc. with some complicated truth tables which depend upon the previous states of inputs as well as the current states (e.g. 'rising:high & rising:high == rising', but 'rising:high & high:falling' == 'unstable unknown'), since the first signal might or might not have gotten high soon enough to generate a high pulse on the output.

  • \$\begingroup\$ Wow, you just gave food for thought. I intend The continuous time sim as well as single time (former in form of truth table, later as a interactive toggle switch input). \$\endgroup\$ – Vinayak Garg Dec 28 '11 at 6:06
  • \$\begingroup\$ @VinayakGarg: Continuous-time digital simulation poses some tricky issues. Many simulations simply assume that the output of a gate will switch at some particular time after the input switches; in some ways, a more useful model would have the output become "undefined" after the minimum propagation delay, and then switch to the correct value after the maximum delay. Although such a model has the advantage that a circuit whose simulation behavior matches what's desired will almost certainly work, there are many designs which would work in practice... \$\endgroup\$ – supercat Dec 28 '11 at 6:47
  • \$\begingroup\$ @VinayakGarg: ...but would in simulation simply have all nodes come up "undefined". Making the model useful while still capturing "worst-case" behavior is somewhat tricky, and requires adding lots of extra states. \$\endgroup\$ – supercat Dec 28 '11 at 6:48

There are generally two approaches simulators can use for something like this:

1) Assign, or assist on the assignment of an initial state

2) Simulate with 3 (or more) state logic, one of which is "undefined" - and have the undefined input propagate through all dependent logic producing undefined outputs. This is a quite common approach - build a state machine in Verilog, put in a statement to have the simulator print the state variable, and see that it displays "x" until everything that factors into that value is defined. (In the case of your Q and /Q, both would be undefined)

  • \$\begingroup\$ +1 i have used VHDL, so maybe it can answer my such questions. \$\endgroup\$ – Vinayak Garg Dec 27 '11 at 14:25
  • 2
    \$\begingroup\$ As a user of such simulations, I prefer 2. Have 'unknown' as a third state, and have it propagate (and in some rare cases, be generated) according to the obvious rules 0 + u = u + u = u, 1 * u = u * u = u. \$\endgroup\$ – Wouter van Ooijen Dec 27 '11 at 14:51

I would go with the raise an error and refuse to simulate.

Having a floating input is never a good idea.

  • \$\begingroup\$ +1 that's the preferred way, but can there be a situation when a user has no way out? \$\endgroup\$ – Vinayak Garg Dec 27 '11 at 11:10
  • \$\begingroup\$ You should, as a matter of course, ground all your floating inputs. Even on parts of the chip that are unused. \$\endgroup\$ – Majenko Dec 27 '11 at 11:20
  • \$\begingroup\$ Please address my one more important concern, i have updated my question. \$\endgroup\$ – Vinayak Garg Dec 27 '11 at 11:27
  • 1
    \$\begingroup\$ @Majenko: it's unspecified. Even if he finds out experimentally, there's no guarantee that it will always do that. (Also, what "floating input" are we talking about?) \$\endgroup\$ – Jason S Dec 27 '11 at 12:50
  • 1
    \$\begingroup\$ @Majenko What happens if you want to initialize the FF 1 uS after the simulation starts? That's a completely valid thing to do in real life(tm). The simulation shouldn't refuse to run. Instead, it should note that the FF is in an undefined state but otherwise simulate. \$\endgroup\$ – user3624 Dec 28 '11 at 2:04

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.