# Multi level logic in transistor level. Possible?

I am currently studying the MOSFET transistor for Digital CMOS IC design. There, the noise ratio is defined and the 50% margin is assigned for a logic HIGH and LOW.

Taking the noise into account, do we have enough room to differentiate 4 level voltages(logic level) in transistor?

So we can achieve four logic levels: 0, 1.25v, 2.5v, and 3.75v

Therefore : Invert(0) = 3.75 and Invert (1.25) = 2.5v

In theory: yes

Is it practical ? No

All circuits are analog

Analog circuits have an infinite number of levels.

Digital 2-level electronics is an abstraction of the behavior of analog circuits. This is done because:

• transistors are on or off, this saves power (current only flows during transitions)
• this is simple, simple logic descriptions are easy to make, simulate, design with
• It is robust regarding noise on the signals and the supply

Using multi level logic would get rid of most of these advantages and it would not bring a lot of advantages.

Multi-level logic would result in more complex and larger circuits, the equivalent 2-level circuit will almost always be smaller and therefore more cost effective. The exception is MLC flash memory but that is not combinatory logic.

Maintaining the "mid-level" voltages requires some current to flow, always, even when the circuit is static. A complex function would result in a very hot chip.

• Of course, to overcome the consumption problem, you could have one supply rail for each voltage level... Wait... Mmh, yeah, it doesn't make things more practical.
– dim
Jun 23, 2016 at 9:30
• How do you design an inverter with two supply rails which can invert all 4 levels as I described then? Jun 23, 2016 at 9:39
• That is not so easy to explain. I guess it can be done with some opamps and feedback resistors. Or voltage comparators. Or sort of a rudimentary ADC converter. Specifying the behavior properly is already complex. You basically need an analog circuit which will be much more complex than its 2-level equivalent. Jun 23, 2016 at 9:55

This technique is used for MLC (multi-level cell) Flash, 1G and 10G Ethernet, and almost nowhere else. The reason is that discriminating among the 4 levels is complex, whereas the simple 2-level system produces gates in which every trasistor is either 'on' or 'off'.

• yes the idea is coming from telecommunication. I was just wondering if could apply it to transistor level circuits. Thanks for mentioning MLC. I didn't know about it. Jun 23, 2016 at 8:59