# Open drain concept in I2C bus?

(I am mainly from a software background and just started to work on an embedded platform. Excuse me if this is a naive question...)

I am planning to write a driver for an EEPROM which is connected to the MCU via an I2C bus. So I am reading a tutorial about the I2C bus.

The tutorial says:

Both SCL and SDA lines are "open drain" drivers. What this means is that the chip can drive its output low, but it cannot drive it high. For the line to be able to go high you must provide pull-up resistors to the 5v supply. There should be a resistor from the SCL line to the 5v line and another from the SDA line to the 5v line. You only need one set of pull-up resistors for the whole I2C bus, not for each device, as illustrated below:

The red part in the above image is added by me. I guess that's how the whole picture is.

My questions are:

• Is my adding of the red MCU correct?
• The bold part the chip is the red MCU, right?
• Why is it true that the chip cannot drive it high? Is it unable or forbidden to?
• What does open drain mean in plain English?

I searched a bit but seems cannot find a clear explanation...maybe an analogy will help.

• Cannot means "must not" here, as in: The I²C spec forbids that. – Turbo J Jun 27 '16 at 6:55
• And almost any I2C interface will also be unable to, because why would they bother making the chip able to do that when it's not allowed to anyway? – user253751 Jun 27 '16 at 10:22
• @immibis Most microcontrollers, actually.... some have all kinds of configurable drive options, and it's not guaranteed to be configured correctly just because the I2C peripheral is enabled -- you need to take care to make sure the pin is configured properly – Daniel Jun 27 '16 at 16:21
• See open collector for an explanation of the terminology. (A bus of this type can be driven either by a bipolar transistor or a field-effect transitor; the terminal of the transistor that's connected to the bus is called the "collector" for a BJT and the "drain" for a FET, but from the bus point of view it's the same thing). – hmakholm left over Monica Jun 27 '16 at 18:49
• @Daniel: If an I2C bus has more than one slave hard-connected to SDA, then it may be possible for the slaves to get into a state where communication will be impossible unless or until the devices are forcibly reset or the CPU is able to raise the state of SDA on one despite the other device trying to pull it down. – supercat Jun 27 '16 at 20:41

Is my adding of the red MCU correct?

Not exactly. The MCU is just another member of the bus like the rest of the Devices. There is nothing particularly special about how the MCU operates on the I2C bus. The MCU can recognize when either line is high or low, and the MCU can pull on either (or both) of the lines itself in order to communicate with all the other devices on the bus.

The bold part the chip is the red MCU, right?

It implies that the MCU is somehow different than the other devices on the I2C bus. But in reality, it is NOT special.

Why the chip cannot drive it high?

If you understood the nature of passive pullup, open-drain busses, you would understand that is not a proper question. You don't WANT any of the devices to drive it high because that would completely preclude any communication on the bus. The devices can only communicate if they can pull the bus LOW so that all the other devices on the bus can recognize that activity is taking place.

What does the open drain mean in plain English?

It is just like the signaling system used on many pubic transportation vehicles. There is a long "rope" along the length of the car, and ANYONE along the line can pull down on the "rope" to signal that they want to get off at the next stop. If you fixed the "rope" so that it was always HIGH, then nobody could pull on it to signal a stop.

• "It implies that the MCU is somehow different than the other devices on the I2C bus. But in reality, it is NOT special." When you're talking about just the hardware, sure.. but this is probably too confusing because the next conversation is about the protocol and who is mastering the bus, which DOES make the MCU special. – Daniel Jun 27 '16 at 16:19
• @Daniel. Yes, I agree completely. But the question appears to be about the OSI Layer-1: Physical Layer. And at that level, the MCU is an equal player with all the other devices on the bus. And remember that the bus master is NOT ALWAYS the MCU. Master status can be transferred to other devices where necessary. – Richard Crowley Jun 27 '16 at 16:38
• Ah the infamous multi-master... difficult to design, hard to debug! ;) – Daniel Jun 27 '16 at 17:01
• The CPU is special, because it's the bus master, and if nobody is capable of pulling SDA high when any device is pulling it low, then a glitch which causes a slave device to get out of sync could leave the bus in a state where nothing would be able to communicate again (e.g. if two EEPROM devices are both full of zeroes, but a glitch causes one to see an extra clock pulse while the master is sending out the read command, then each device will release SDA for one out of nine cycles, but they'll never both release it simultaneously. – supercat Jun 27 '16 at 20:59
• 1) The CPU is not always the bus master. Any device on the bus can be the master. So the CPU is NOT special in that regard. 2) The question appears to be asking about the PHYSICAL LAYER, the passively pulled-up bus with the open-source devices. Again, in that regard the CPU is exactly like every other device on the bus. If we think the quesiton is about the Data Link Layer or the Network Layer then we need @smwikipedia to return and clarify the question. I am refering to the 7-layer model: en.wikipedia.org/wiki/OSI_model – Richard Crowley Jun 27 '16 at 21:08

"The chip" refers to any I2C device; generally, the master will drive the clock, but SDA is bi-directional as the slaves have data to transmit back. Therefore both the master and slaves are capable of tugging on SDA; advanced devices may also be able to toggle SCL in addition to the master.

A simple analogy for open drain is a bus, and the rope / harness you use for signaling the driver for a stop. Everyone on the bus can yank on it and pull it down, but tension in that line will pull it back up after you release it. The strength of the pull up + the capacitance in the line will determine how fast you can run.

Electrically, it's generally a pin with a N-channel MOSFET that can be turned on to sink current and pull the line low. Releasing the FET / turning it off allows the pull-up resistance to restore the bus value to '1'.

• SCL signal is also bidirectional: The slave can 'stretch' the clock by keeping the SCL line low. – Turbo J Jun 27 '16 at 6:54
• Looks like that's the usual analogy, but I hadn't seen it before - great comparison! – underscore_d Jun 27 '16 at 10:57
• Another one that's amusing is a series of toilets, and you can only flush them for communication -- the time it takes for the water to fill the bowl back up is similar to the RC constant of the bus as well. – Krunal Desai Jun 27 '16 at 16:41

My questions are:

• Is my adding of the red MCU correct?
• The bold part the chip is the red MCU, right?
• Why is it true that the chip cannot drive it high? Is it unable or forbidden to?
• What does open drain mean in plain English?

I searched a bit but seems cannot find a clear explanation...

A pretty clear one is here (which is where Wikipedia takes you if you type in "open drain").

The open collector (BJT) or open drain (FET) is essentially a SPST switch connecting the IC pin to ground. If the switch is closed, then the voltage on the pin (and the I²C line) is about 0 volts. If any switches are closed (if any pins of any ICs are connected to the same SDA or SCL line), the voltage on the line is about 0 volts. Only if all of the switches are open is the voltage on the line high (like 3.3 V) and that's why the line requires a single pull-up resistor.

Sometimes they call this a "wired-OR" or "wired-NOR", but it seems to me to be most accurately called a "wired-AND". The value of the line is 1 if and only if all of the outputs are logic 1. If any output goes to logic 0 the entire line goes to 0.

That's what open drain means. Your red MCU is just another I²C device except it might be the sole driver on the wired-AND SCL line unless clock stretching is happening (any of the other I²C devices can hold the SCL line low if they want to and that should hold back the read or write cycle on the SDA line).

It is both true that any I²C chip can not and must not drive the SDA or SCL lines high. The only thing that can pull the lines high are the two pull-up resistors connected to +VDD.

(Thanks for all the replies so far. After days of reading the I2C tutorial and various related materials on the SparkFun site, all these replies start to make sense to me now. And below is my own summary.)

## Open-Drain Or Open-Collector

This jargon just described how the circuit is built. Just as described in robert bristow-johnson's link, the open-drain/collector circuit has a BJT/MOSFET between the real IC output signal and the exposed IC pin. It is the BJT's collector or the MOSFET's drain get exposed (I think this is what the open is meant for). And a pull-up resistor is usually connected to the pin externally to the IC. As shown below:

It is the resistor pulling up the voltage rather than the IC offering a high voltage signal, so I guess this is what Richard Crowley mean by passive pullup.

## Bus Contention

If all the devices' output pins on the line are using this circuit, it will be impossible for some voltage drop to happen between 2 device pins. So no 2 devices will be short circuit.