I've been looking through a bunch of designs I found online on LPDDR2 interfacing. What's always confused me is the parallel decoupling capacitors. Why have so many vs just combining that to what you want. Also how do you figure out what value you want for the total capcitance?
There are two options depending on what is in the rest of the circuit.
Firstly, having multiple capacitors in series reduces the ESR, which in high frequency applications can be critical for decoupling.
Secondly, and in this case more likely, frequently ICs have multiple power pins. Even if these multiple pins are connected to the same supply, ideally we want the decoupling to be as close as possible to the supply pin to keep the AC current return path as short as possible. If there are multiple pins, this implies we need a capacitor on each one.
In both cases the multiple capacitors are frequently grouped together in one place in the schematic to keep things readable.
Different capacitors have different resonant frequencies, so they are good for filtering different frequencies.
Using more than one bypass capacitor will therefore expand the range of frequencies that will be filtered out.
This video tutorial answers your question in more detail: