# Clock Domain Crossing for Pulse and Level Signal

For pulse we use Pulse-Synchronizer and for Level Signal we use 2-flop synchronizer but what if the signal can be of Pulse or Level behaviour. Is there any way to synchronize that?

EDIT:

After @Paebbels's answer, there is modification in Circuit, it should be like that, signal transformation is in tx-clock domain instead of rx-clock domain.

and its simulation is like below,

But now issue is to transform number of cycle on tx-clock side to rx-clock side. Atleast level CDC will converge to level at rx-clock domain, we can remove the constraint of number of cycle transformation.

• Can you show the basic circuit architecture of your two synchronizers? Sometimes the 2 or 3 flop synchronizer can pass a pulse if the pulse is wide compared to the clocking rate of the flops. Then you can apply edge detection techniques at the output of the synchronizer to create the pulse when needed. – Michael Karas Jun 28 '16 at 12:39
• @MichaelKaras I want circuit works with irrespective of knowing clock rate, so your assumption of to generate pulse at output synchronizer is not fulfil criteria. – Prakash Darji Jun 29 '16 at 3:52

You can add an edge-detection to the pulse/strobe synchronizer.

How does a normal pulse/strobe synchronizer work?

1. If it supports a busy signal, then the input is blocked until the circuit is ready
2. The signal is transformed from impulse to a level change by a T-FF (D-FF + XOR)
3. The level/flag signal is transferred to the other clock domain by 2 D-FF
4. The impulse is restored by another XOR gate and a delay (D-FF)
5. 2 more D-FF are transferring the signal back to the source clock domain, so a busy signal can be derived (XOR).

What can happen to this circuit, if pulses are forming a constant signal?

The circuit will start to toggle and generate many pulses on the output.

Solution:

This toggling can be stopped by adding an edge-detection on the input (D-FF + NOT + AND) or if the sender complies to the busy signal.

simulate this circuit – Schematic created using CircuitLab

Source: PoC.misc.sync.Strobe

• Thanks for your clear explanation, I will write Verilog code and see it works or not, also I will make sure it follow CDC rules, and let you know. If any problem is there. – Prakash Darji Jun 29 '16 at 3:54
• You are targeting an ASIC? Make sure to use proper flip-flops for the 2-FF synchronizer, which are better suited for meta-stability. In our FPGA solution, we are using either vendor primitives + constraints (Xilinx ) or VHDL attributes (Altera). For example, you may need to disable shift register extraction, otherwise the synthesis might combined these 2 FF to a little shifter with poorer meta-stability properties. We are also using relative placement constraints, to restrict the path length between these 2 FF. P.S. See our other sync modules, for synchronizing more than 1 bit signals :). – Paebbels Jun 29 '16 at 7:45
• Yes, I targeting for ASIC and FPGA both. But forth now concern is only method, and you have explained it very well. – Prakash Darji Jun 29 '16 at 10:44
• Are you sure your "Signal Transformation" block will not affect by metastability? – Prakash Darji Jun 29 '16 at 11:41
• because output of XOR will be combinational and depends on signal (You mentioned at that point "changed_clk1") which is async and may affect that FF. – Prakash Darji Jun 29 '16 at 11:52

Depends on what information about the signal is important. If you have something that can be either a relatively constant level as well as relatively short pulses that are closely spaced, then what you may need to do is use an asynchronous FIFO and store the value of the signal in the FIFO when it changes. Level and pulse synchronizers only work well with 'sparse' signals that don't change very often. However, if your pulses are at least several clock cycles long, a level synchronizer might be just fine.