For pulse we use Pulse-Synchronizer and for Level Signal we use 2-flop synchronizer but what if the signal can be of Pulse or Level behaviour. Is there any way to synchronize that?
After @Paebbels's answer, there is modification in Circuit, it should be like that, signal transformation is in tx-clock domain instead of rx-clock domain.
and its simulation is like below,
But now issue is to transform number of cycle on tx-clock side to rx-clock side. Atleast level CDC will converge to level at rx-clock domain, we can remove the constraint of number of cycle transformation.