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I have a custom IP created with 2 output pin (en1_out and dir1_out) enter image description here

May I know how to map these two pin to the PMod pin on FPGA (pin Y11 and pin AA11)? I have tried to open the elaborate design and in the I/O Ports I can't find these two pin.

enter image description here

I am using ZedBoard and Vivado 2016.1 Thank you!

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Are they broken all the way out to your top-level design? If not, you have to define some external ports in your block diagram, and then assign them in your constraints (XDC) file. Otherwise, those pins will remain internal / not-connected.

Right-click in the BD, and create a port (Ctrl+K):

enter image description here

Then, when you auto-generate the wrapper for the block diagram, the new port should be present for you to connect to.

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  • \$\begingroup\$ Thank you for your prompt reply. I will try it out and give you a reply as soon as I get it working. Thanks! \$\endgroup\$ – user9870 Jun 28 '16 at 22:22

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