Looking for help answering a few question about choosing parameters for a small voltage doubler circuit.

I'm looking to prototype a USB powered random number generator based on the shot noise of a Zener diode just entering its breakdown region. I understand the best noise is from Zener's with a breakdown above 5 volts, so I think I need a voltage doubler. I'm hoping to drive the voltage doubler with the signal from a GPIO port on the PSOC 5LP, and measure the output using a second pin. I found a nice old article from 1998 a similar approach, but I think it can be done with far fewer components today.

The article said: "Optimum noise performance is obtained from a 1N753A Zener diode, which has a 6.2-V Zener 'knee.'" It also mentioned that the optimal current for noise output was about 20 uA, generating about 20 mV p-p noise.

Based on this idea I've sketched out this circuit ZRNG by BurtHarris 32c9f7a0565893b5 - Upverter

So my questions are:

Does driving this from a GPIO port make sense?

Any reason I should try to make the drive approximate a sine wave, or can I just hit it with square wave like digital output?

Is there any limit to the frequency I should drive it at? I understand that higher frequencies will reduce the size capacitors I need.

With a frequency chosen, how do I size the capacitors.

P.S: Note that part of the design goal here is to have the SoC chip adjust the "doubled" voltage to optimize the noise generated. It won't need to fully double VCC.

  • \$\begingroup\$ I may have the diode polarity reversed... \$\endgroup\$ Jul 1, 2016 at 0:31
  • \$\begingroup\$ Of course, and constructive criticism would be welcome. I consider the voltage divider and sense line optional and probably just implemented in the prototype. \$\endgroup\$ Jul 1, 2016 at 0:47
  • \$\begingroup\$ I've come to realize that the frequency and capacitor sizing question have an additional constraint: allowable ripple. Because the broadband noise generated by the Zener diode is on the order of 10 mV, I started to think I would need to keep ripple down to 0.1 mV, but I'm considering on another approach that wouldn't be so sensitive to ripple. Thanks for all the help guys. \$\endgroup\$ Jul 2, 2016 at 18:44

2 Answers 2


Mark got everything right except to note that the anode of D3 has to be connected to +5V. Then when the PWM is low,C4 gets charged. When the PWM is high, that charge appears in series with the PWM output, hopefully about double.

Another approach to consider would be the venerable old 7660 or one of it's successors; it doesn't add much (if anything) to the complexity, and you have all kinds of design information oh the data sheet(s).

  • \$\begingroup\$ And I would second the idea of the 7660. You can trust it to work. \$\endgroup\$
    – Mark
    Jul 1, 2016 at 1:15
  • \$\begingroup\$ As far as I can tell, without simulating, tying the anode of D3 to +5v does work. \$\endgroup\$
    – Mark
    Jul 1, 2016 at 1:18
  • \$\begingroup\$ Hmm. I'd have to split the bottom rail in the diagram to keep the Noise signal's DC average where I want it, making it look like this: ![ZRNG by BurtHarris 32c9f7a0565893b5 - Upverter](upverter.com/BurtHarris/32c9f7a0565893b5/ZRNG/#), which I think will work. But none of this answers my questions about choosing working frequency and capacitor sizes. \$\endgroup\$ Jul 1, 2016 at 2:00
  • \$\begingroup\$ Updated diagram in question. Thanks for the input, still looking for answers about operating frequency and sizing capacitors. \$\endgroup\$ Jul 1, 2016 at 2:06
  • \$\begingroup\$ P.S. I looked at the 7660, it seems like overkill. Its a 50W converter, and I need less than a milliwatt. \$\endgroup\$ Jul 1, 2016 at 2:24

I don't know anything about the zener-noise portion of your circuit, but having used voltage multipliers, I can offer some experience.

The point is to fully charge the capacitors, and then reverse the polarity as soon as they are charged. So you would size the capacitors based on your voltage and switching frequency (necessary, if you use 60Hz line frequency), OR select your switching frequency based on your voltage and the size of the capacitors (your best bet, since PWM is an MCU). You can watch the capacitors charge on a scope while you tweak the frequency, to optimize performance.

A square wave charges faster than a sine wave, because the charge voltage stays at its peak. Assuming a 50% duty cycle, the current that your doubler will deliver will be less than half of what the PWM pin can provide (because it's half-wave).

However, I don't think that your circuit is configured correctly (yet). I can see caps charging when PWM is high, but nothing when it is low (I'm assuming PWM swings between Vcc and GND). Normally, a doubler's input would swing both positive and negative, and C4 would then charge to the opposite polarity when PWM is negative. That charge would then be pumped into the next capacitor stage (C1).

A solution would be to remove the ground from the circuit, and instead drive that node with PWM/ (an inverted form of PWM). Of course, then "sense" is only valid when PWM is high and PWM/ is low.

BobU has the best fix: tie the anode of D3 to +5v.

In the discussion to follow, I'm ignoring the diode drops. However, when operating at such low voltages the diode drops would have a significant effect on the final voltage. Schottky diodes would be appropriate.

Regarding the capacitor size, there is a relationship between the cap size and the switching frequency. The GPIO pin needs to charge the first capacitor, and we'll assume the the charging current is constant, at the maximum that the pin can source and sink. So the energy in the capacitor will increase linearly. If you wait until it is fully charged before switching polarities (and dump that charge into the next stage), you will get maximum voltage (real "doubling", ignoring diode drop). The available current comes from the GPIO pin, but will stop flowing once the capacitor is full. If you switch polarities before the cap is full, you won't get the maximum available voltage. If you switch later, then you won't get the maximum available current.

An estimate of the available current would be:

[(GPIO max source current) + (GPIO max sink current)] / 2

That would assume a 50% duty-cycle. If the source and sink current are very different, it would be worthwhile to adjust the duty-cycle to balance them.

Here is a handy formula:

1 mA constant current increases the voltage on a 1 microfarad capacitor by 1 volt in 1 millisecond.

Since you have .02 uF caps and 5 volts, then 1 mA will charge the cap in 100 microseconds. That would equate to a 5 kHz PWM frequency. Your frequency will probably need to be faster, as your GPIO pin probably provides more than 1 mA. If you double your cap size, you would halve your frequency (double your charge time).

The actual charge current from the GPIO pin won't be specified with any accuracy, so you may need to optimize dynamically. Since you have a "sense" pin, one approach would be to start the switching frequency too high, and watch the voltage rise as you bring down the frequency. You would then stop decreasing the frequency once you sense your desired voltage.

  • \$\begingroup\$ Being USB bus powered, I've got just the single-ended +5 and ground available. I was assuming what mattered about the drive was it's AC content, rather than going above and below ground. I certainly could be wrong about that. \$\endgroup\$ Jul 1, 2016 at 1:02
  • \$\begingroup\$ But when PWM is low, no current flows. I have updated the answer with a potential solution. \$\endgroup\$
    – Mark
    Jul 1, 2016 at 1:06
  • \$\begingroup\$ The idea about removing the ground seems interesting, but confusing. I want to ensure that the "Noise" signal at the top of R1 is within the 0-5 volt range the SoC can work with, if I remove the ground and replace it with a inverted PWM signal, I think it the Noise signal might drift up past the input limits. \$\endgroup\$ Jul 1, 2016 at 1:07
  • \$\begingroup\$ Ah, yes. I see the problem there . . . \$\endgroup\$
    – Mark
    Jul 1, 2016 at 1:08
  • \$\begingroup\$ I think the current flow happens during the transitions, not when the drive signal is at a static level. The point is that as PWM transistions from high to low, current flows through D3, and low to high causes current to flow through D4. \$\endgroup\$ Jul 1, 2016 at 1:10

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