How is the circuit supposed to work?
I'll refer to the designators in the patent drawing.
First, normal operation:
By KCL at node (36), the sum of the currents through D1 and D3 must be equal to the current provided by the current source (30). Similarly, the sum of the currents through D2 and D4 must be equal to the current sunk by current source (38).
Now when I1 produces a current, it will increase the current through D2 and decrease the current through D1. So that means the the current through D4 must decrease and the current through D3 must increase.
Now the current through D4 and D3 are not equal, so by KCL at node (46), some current must flow into the op-amp circuit through R1. This current will be equal to the current originally produced by I1.
Now, overload operation:
Because of current source (38) (let's call that "I38") the maximum current through D2 is limited. If the current from I1 is greater than I38, it can't flow through D2, and it can't flow through D1 because it would be reverse from the diode's direction. So the voltage at node (48) must rise until the JFET (52) is activated to pass current in diode operation, and the excess current flows through the JFET. Meanwhile, the current imbalance between D1 and D2 is limited to I38, so that is the current that gets delivered to the op-amp circuit.
Why is your simulated circuit probably not working?
According to the datasheet, LT3092 works when there is a positive bias of between 1.2 and 40 V between the input pin and output pin.
Your circuit provides no such bias. If the input node voltage (node (48) in the patent drawing) is positive, then your U4 might operate correctly, but U2 will not. If the input node is negative, then U2 might operate correctly, but U4 wil not.
A likely solution is to provide either a positive bias at the IN pin of U2, or a negative bias at the output of U4 (where R10 and R11 are joined).