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For me there is no doubt that one of the most time consuming tasks when it comes to produce a new board is going from a ratsnest to the final layout. I must admit I am not an expert, but to me it takes days, and I would never ever be able to do it without the aid of Kicad, even for circuits of modest complexity. It would be very interesting for me to know how it was at the beginning, when EDA (electronic design automation) software didn't exist at all. Which was the technique, which were the tools? I'm convinced one should learn how to do math with paper and pencil before using a calculator, this is why I'm asking.

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  • \$\begingroup\$ Very very interesting! Thank you all for your answers! \$\endgroup\$ – Enrico Jul 1 '16 at 14:51
  • \$\begingroup\$ Even with EDA, I sometimes find it is faster for very small single sided boards to use the 1990's equivalent of tape and dot, Paint or some equivalent low-level graphics program. The ability to clone shapes from a private library of SOIC footprints, draw lines of a certain width etc, we don't need no stinkin' design rule checkers!!! \$\endgroup\$ – Neil_UK Jul 1 '16 at 15:19
  • \$\begingroup\$ One step was to draw a tidy schematic using the actual package pinouts. This would help skip the 'ratsnest' stage, as it was very hard to move the IC footprint stickers. (I can remember cutting out sections of vellum or mylar to move a good piece of tape work to a new spot to allow squeezing in more parts or traces). \$\endgroup\$ – amI Jul 1 '16 at 19:17
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Before computers were cheap and available enough to be used for such things, a "layout person" (a specialty of draftsman) would manually design the board layout. This was done on a drafting table at larger size than the real board. The engineer provided a D-size schematic to generate the board from.

The layout guy would lightly pencil in tracks, then use special tape over the rough sketches. This tape was black and similar to masking tape. It came in rolls for pre-determined trace widths at specific enlargement ratios. For example, you'd have a roll of "20 mil" tape to be used at 4x enlargement, so the tape was actually 80 mils wide. There were also adhesive sheets to be cut with a exacto knife for arbitrarily shaped copper areas. As WhatRoughBeast mentioned in a comment, there were also various pre-made adhesive patterns you could buy for various enlargement sizes. Examples were the footprint of a 14 pin DIP, a TO-92 package, and the like. These made some of the grunt work easier and less error-prone.

The finished taped drafting sheet was then used photographically to make the transparencies that were used to manufacture the board. Actually there was a finished taped sheet for each PCB layer.

It might take two weeks for the layout to be finished for maybe a 40 square inch board, depending on complexity, of course. After that the layout guy and engineer would spend a day "roadmapping". The layout guy would start on one pin of one part, then follow the traces and call out all other part pins encountered, marking the traces as checked. The engineer would follow along on the schematic, marking connections as checked. This is how missing and erroneous connections where found.

After roadmapping, usually a day or two of more layout work would be required to fix problems found, then more roadmapping, etc.

However, all that is ancient history. While interesting as history, it really isn't relevant today. It's so much nicer to use a integrated schematic and board design package where the software guarantees that the final layout matches the schematic.

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    \$\begingroup\$ You should also mention the self-adhesive IC package pads, available at 2x and 4x sizes. These were opaque pad patterns on a transparent backing which could be laid on the Mylar sheet. Available in DIP and TO patterns. Also worth mentioning is the use of a grid (0.1 spacing in my experience) under the sheets to keep everything square and on a uniform spacing. \$\endgroup\$ – WhatRoughBeast Jul 1 '16 at 14:41
  • \$\begingroup\$ @What: Good point, added. \$\endgroup\$ – Olin Lathrop Jul 1 '16 at 14:45
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For Tranceiver design, At Motorola, circa 1976, the electronics design engineer would work with a draftsman.

A product called Rubylith was used. Exacto-knife was used to cut away areas. The remaining Rubylith would be where copper foil was intended.

I can't remember what scale we used. I believe we did the the scale either 8 to 1 , or 4 to 1.

Very tedious.

Apparently Rubylith is still available today :

Rubylith

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PCB layout was done by hand on transparent sheets several times the actual size of the PCB. Usually using colored tape on light tables. Photography techniques were used to reduce the size creating high contrast 1:1 negatives used to "print" the PCB.

I think these people are making an Integrated Circuit instead of a PCB. But you get the idea ... tedious:

enter image description here

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There were a couple of different processes that were used in the days before CAD programs.

One of them was rubylith, which was a thin red film over top of a mylar sheet. This was a negative process, where the rubylith film was cut away to make the tracks and pads.

Another process was called tape and dot. It was a positive process where the tape was laid down to create the tracks and the dots were used to create the pads. This was done at a large scale to achieve more precision, then the layout would be photographed and reduced in size to the required scale.

See this article in EETimes

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Oh yes! I remember my early days as an engineering technician, where an engineer would hand me a schematic on "D" size sheet of .1" grid vellum an I would have to build a breadboard from it. Sometimes it would be on an actual blueprint. I would have to procure the parts and either wire wrap a board for digital or create an "airplane" breadboard built on the desired board size with appropriate connectors in the right places to fit into a prototype. Then I would try to make it work on the bench before it ever went to drafting for PCB design. My job would be to debug it and find any of my own or the engineer's mistakes and correct them accordingly. It became far easier with the advent of computerized EDA programs that could simulate the circuits and go to a finished PCB layout in no time. The "olden days" were fun, but nowadays, most circuit simulation is fairly robust and locates problems well before going to the PC board house, which is a great time saver. Nonetheless, there are certain situations where simulations will not resolve when breadboard prototypes are still in order. I learned this in a seminar put on by Bob Pease of National Semiconductor. I was quite surprised by the conditions in which computer simulation will not yield an answer, and the simulated circuit actually does not work but works when in breadboard form. Bob was National's chief scientist and when he died, the industry lost a true genius in the analog world.

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