Is it possible to efficiently infer a RAM with "peek" ports apart from the usual standard ports?

A 32-bit x 4 RAM might have a peek port to peek at data just ahead of the current data being accessed by the read address. Approximate code would be...

assign peek = mem [ (rd_addr + 1) & 2'b11 ]; // RAM peek port (read).


apart from the stock RAM code...

reg [31:0] mem [3:0]; // 2D array.
always @ (posedge clk) if (wr ) mem [ wr_addr ] <= wr_data; // Write.


It would be nice to infer a SINGLE block RAM with some extra (very simple?) read circuitry (ISE infers 2 RAM blocks). I guess this shouldn't require a true dual read port RAM (independent read circuits) or RAM duplication since the read addresses are always related (always 1 ahead). Is there an area efficient way of implementing the above in a typical modern FPGA ?

EDIT: Forgot to add write enable!

EDIT: This RAM is intended for video decoding. Example a stream of pixels received as 0x1234_5678 0x023_45678, 0xAAAA_AAAA would be decoded as 0x1234 (16-bit upper), 0x5678_23 (lower 16-bit + 0x23 from next, initial 0x0 is skipped), 0x678A_AAAA etc (0x45 is skipped). The decoding algorithm is derived from an LFSR that maps to the transmitter and changes for every pixel.

• If ISE infers two RAM blocks is because you made an incomplete model of the RAM... how do you thing the second block would be updated when you need to write to the RAM? If BW is the issue, you can burst access the RAM. – Claudio Avi Chami Jul 1 '16 at 17:12
• @ClaudioAviChami, oops! forgot to put a write enable. – Revanth Kamaraj Jul 1 '16 at 18:52
• Because you forgot you received a 'simple' solution. A real solution is more complicated because you have to take care of writing to both RAMs. – Claudio Avi Chami Jul 2 '16 at 5:04
• @ClaudioAviChami, I don't want to write to 2 RAMs, I want a single RAM with an extra read port instead of writing to 2 RAMs in parallel. I don't think the complexity of a true dual port RAM or RAM duplication is required since the 2 read addresses are always related in a very specific way. My guess is that FPGAs do not provide native implementations of lookahead RAMs (like AndyW mentioned) and must be implemented using LUTs. – Revanth Kamaraj Jul 3 '16 at 15:52
• at the FPGA level you simply can't do that. If you were making an ASIC (maybe) you could access the RAM cells and do the trick. On an FPGA a single-port memory is a defined block where there is a single data bus that reflects the contents of the last requested address. There is no other data bus available, and no LUTs will be able to access data that is not at the RAM port. Any solution to do what you want demand a dual port RAM. – Claudio Avi Chami Jul 4 '16 at 3:47