Is it possible to efficiently infer a RAM with "peek" ports apart from the usual standard ports?
A 32-bit x 4 RAM might have a peek port to peek at data just ahead of the current data being accessed by the read address. Approximate code would be...
assign peek = mem [ (rd_addr + 1) & 2'b11 ]; // RAM peek port (read).
apart from the stock RAM code...
reg [31:0] mem [3:0]; // 2D array. always @ (posedge clk) if (wr ) mem [ wr_addr ] <= wr_data; // Write. always @* rd_data = mem [ rd_addr ]; // Main Read.
It would be nice to infer a SINGLE block RAM with some extra (very simple?) read circuitry (ISE infers 2 RAM blocks). I guess this shouldn't require a true dual read port RAM (independent read circuits) or RAM duplication since the read addresses are always related (always 1 ahead). Is there an area efficient way of implementing the above in a typical modern FPGA ?
EDIT: Forgot to add write enable!
EDIT: This RAM is intended for video decoding. Example a stream of pixels received as 0x1234_5678 0x023_45678, 0xAAAA_AAAA would be decoded as 0x1234 (16-bit upper), 0x5678_23 (lower 16-bit + 0x23 from next, initial 0x0 is skipped), 0x678A_AAAA etc (0x45 is skipped). The decoding algorithm is derived from an LFSR that maps to the transmitter and changes for every pixel.