Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good reasons for this bias in the industry?
It is not so much a 'bias' in the industry as it is a matter of design strategy. Two high-speed clocks 180 deg out of phase (clock A and clock B) sounds like a good solution for input register/output register(or count and store)clocks or to prevent race conditions.
At low speeds less than 500MHZ a 2-phase clock is not such a big issue, but at GHZ clock frequencies it is near impossible to prevent skewing of clock A compared to clock B, especially after traversing through several turns and layer shifting. This quickly renders the 2-phase scheme useless, as the skewing would have to be constantly corrected.
Better to have a single master clock and use 'point of use' delays where needed for data setup and hold time, register read time, etc. Single edge flip-flops only latch data on the rising or falling edge of the clock. For longer delays a nand latch can 'trap' the clock pulse until it is used, which resets the latch. Often this 'point of use' delay is just a zig-zag pattern in the trace right at the IC that needs the delay.
With attention to details, the rising edge can be used to latch an address into a dram/ram/register and the falling edge can be use to read or write data. As long as the address/data is stable before the clock edge arrives (even by a few hundred picoseconds), this helps the single-phase clock scheme work at its best.
CPU's and MPU's still use a 4-phase clock but only in the state-machine core, to perform the 'fetch/decode/execute/store' procedures in an orderly fashion. Note that some modern CPU's may use a 6 phase clock so that pre-fetch and write-back are added to the sequence.