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I want to use a bunch of cascaded M74HC595B1R shift registers in my project. VCC will be 5V, clock frequency 8-10 MHz. Outputs of these registers will be driving gates of 2N7000 N-MOSFETS if that matters. My questions are

  1. Should I install decoupling caps for my shift registers and what value if yes?
  2. VCC and GND pins are rather far apart on the opposite corners of package. Does it matter if I physically place the cap as shown with red lines (unequal distances to VCC and GND pins) or as shown with blue lines (equal distances from pins on the opposite side of the board) Decaoupling cap placement variants
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  • \$\begingroup\$ Neil_UK's answer is more than definitive, but I'll add that if there isn't anything competing on the underside of the board, you might want to favor the 'blue' path - it conserves space on the top IC side of the board which will help with board density. \$\endgroup\$ – ecfedele Jul 2 '16 at 10:04
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In addition to the other answers (yes you should use decouplers), the path length (so you can use the optimal path) for decoupling needs to be short relative to the output transition time.

ST has helpfully included that information in the datasheet:

M74HC595 output transition times

Note that these are not propagation delays (which are listed beneath).

The name of the game in decoupling is to ensure that the decoupling path is short enough to not cause power pin droop due to transition effects; taking 0.1 of the output transition time determines a safe distance for the decoupling path.

Using the shortest time of 6ns is informative.

6nS on FR4 is about 3 feet, so getting to 10% of that (a useful rule of thumb) means the path should take less than 3.6 inches. The manhattan distance between the Vcc and ground pins on the device is just over 1 inch.

Even using the option on the left will not bring the decoupling path anywhere close to having any issues, so from a PCB decoupling perspective, either solution works.

[Update]

Although this device lists transition times in the datasheet, many do not; newer devices will usually have an IBIS model which has (amongst other things) the same information in most cases.

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  • \$\begingroup\$ Thank you for enlightening me about using output transition time for estimation of critical decoupling path length. Really appreciate that. Your answer will let me solve problems like that myself. That is why I will accept it. Sorry Neil_UK and TonyM. I would have accepted your answers too if I could. You gave me direct answers with cap values and pointed to some potential problems of my scheme but I value ability to solve problems myself without bothering others most. \$\endgroup\$ – Fedor Kotov Jul 2 '16 at 17:49
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You definitely should have decoupling capacitance on your board. I would recommend a 100 nF ceramic or similar per IC.

You also should have bulk decoupling capacitance distributed across the circuit, as befits the load on the gate outputs and the distance to the source power supply. For myself, I would put a 10 uF capacitor for every 3..5 ICs. I would also have a 47 uF capacitor by the power supply, be it local regulator or input connector.

As an aside, will you have a series resistor between each IC output and its loading FET gate? Otherwise, on an IC output rising edge, it's trying to charge the gate capacitance which first appears as an instantaneous short and dips your rail. The resistor limits the gate charging current and gives your IC a better life.

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  • \$\begingroup\$ Thank you for overall decoupling strategy recommendations. Yes I intended to put 100 Ohm series resistors for each FET gate. \$\endgroup\$ – Fedor Kotov Jul 2 '16 at 17:23
  • \$\begingroup\$ @Technocrat, you're welcome and great, you're already limiting your gate charging current. Maybe worth considering a resistor nearer (5V+10%-0.3)/0.004mA = 1300 R. Either way, good luck with building it :-) \$\endgroup\$ – TonyM Jul 2 '16 at 17:38
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Yes, you should install VCC decoupling caps. 10nF will be adequate as you are only driving a light load.

Given the size of the chip dominates the loop inductance of capacitor, it does not make a huge difference which connection path you choose.

If you do have problems with your scheme, it will more likely come from trying to distribute the 10MHz clock and latch signals to 'a bunch' of 595s. There are several ways you can get this wrong and get poor clocking, depending on how many and how physically distributed 'a bunch' is. Perhaps that should be the subject of a different question.

Parenthetically, the 2N7000 is not a 'logic level' FET. It will work, and it is specified at 4.5 and 5v, but it is better specified at 10v. There is little difference between the maximum 5ish ohms RDSon, but the typicals are fairly different.

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  • \$\begingroup\$ Thank you for direct answer to my questions. I explained why I accepted Peter Smith's one and not yours in a comment to his answer. 'A bunch' is 9 in my case. I understand that I will probably have some problems with 10 MHz clock. High clock rate is desirable but not absolutely critical. This way I hope to get more free MCU cycles for other tasks apart from pushing bits to shift registers. This is one-off a hobby project and I just happen to have a lot of 2N7000s. High RDSon is acceptable I think because they will conduct only about 20 mA. But thank you for pointing this out. \$\endgroup\$ – Fedor Kotov Jul 2 '16 at 18:28

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