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In learning about reducing a circuit's EMI emissions, I've learned the importance of a ground plane, in that it allows the current-return for an AC signal in an adjacent layer to flow directly under that signal's trace, due to that return-path having the lowest inductance due to the smallest loop area, which also consequently reduces EMI.

What I'm now wondering is, what if something gets in between the two layers in question? Particularly, what if I have a power plane or power traces in between my signal trace and the ground plane which allows its current-return?

I've learned that the return current may in fact (confusingly) hop between ground and power planes by any decoupling capacitors along the way. See here. This doesn't sound quite ideal, so I'm considering not having a power plane at all, and instead simply running power traces where I need them. However, I'm wondering whether anything bad will happen if I run a power trace on a layer between an AC signal and its return path. Consider this example, crudely depicted:

PCB stack-up

Firstly, will the presence of the (yellow) power line disrupt the depicted current return path?

And secondly, perhaps more worryingly, the yellow power trace is travelling directly through the "loop" formed between my trace (red) and its current return path on the GND layer, presumably then being subjected to the resulting field (electro-magnetic?) that occurs within this loop. Will that field then induce extra AC currents in the power trace?

Or is there a better way to route power - should I route it on the surface layers only, and have the inner layers as GND only?

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  • \$\begingroup\$ The only problem is that the red trace may couple to the yellow trace. If they cross at right angles it will be minimal. If the Power layer is a power plane, then it is basically just as good as a ground plane. \$\endgroup\$ – mkeith Jul 4 '16 at 0:53
  • \$\begingroup\$ @mkeith if the yellow trace was really wide though, would this affect the return path? As its copper would block the field from the red signal trace from reaching the GND plane for a portion of it, would the return path still "know" where to go, in order to stick close to the red signal trace? \$\endgroup\$ – beammy Jul 8 '16 at 14:23
  • \$\begingroup\$ If they are traces crossing at right angles, minimal effect. The electric field lines wil be traveling through the yellow trace somewhat vertically. \$\endgroup\$ – mkeith Jul 8 '16 at 15:59
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A power plane is just as good a reference plane as a ground plane, and will serve as the reference plane/return path for its adjacent signal layer as its just as good an AC ground as the ground plane is -- so there's no reason to do the routing convolutions you describe.

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  • \$\begingroup\$ Only so long as there are decoupling capacitors between the power plane and ground at both ends of the signal trace, right? If the return currents wants to travel in the power plane, it needs to "hop" there from ground through a decoupling capacitor, and then "hop" back through another one at the other end, is that correct? \$\endgroup\$ – beammy Jul 8 '16 at 9:52
  • \$\begingroup\$ @beammy -- no, see Figures 10-34 and 10-35 of Electromagnetic Compatibility Engineering along with the accompanying text in section 10.7.1 \$\endgroup\$ – ThreePhaseEel Jul 8 '16 at 11:42
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For boards with lots of high frequency routing requirements the problem is solved by using more layers and assign more of them to be ground planes. For example a 6 layer board may use a stackup like this:

  1. surface routing layer
  2. reference ground layer for 1 & 3
  3. inner routing layer
  4. power plane (may be segmented if more than one voltage rail)
  5. reference ground layer for 6
  6. surface routing layer

With such scheme the spacing between layers 1-2, 2-3 and 5-6 is selected so that the trace impedance to the reference ground plane can be controlled according to requirements. For stackup symmetry the 4-5 spacing is often made equal to the 2-3 spacing. The 3-4 spacing is made at least three or more times larger than the other spacings and becomes the predominant core of the finished board and is typically adjusted to arrive at the overall desired board thickness.

Most board manufacturing shops can customize the layer spacing to suit the needs calculated for a given board layout design. However since many readers here are engineers dealing with low volume board manufacturing or hobbyists looking for lowest cost it becomes necessary to ask the prototype PCB shop what standard stackups that they have BEFORE you start your layout design. You then use those numbers when calculating the trace widths to achieve the required trace impedance to the reference planes. Be aware that not all of the prototype shops use the same layer stackup so be aware that a trace impedance controlled design for one shop may not work properly if the production is moved to another shop that uses different numbers in their default stackup.

When using a particular stackup design it is a really good idea to include a fabrication drawing with your board artwork collateral that explicitly calls out the stackup spacings. Also if you are in the low volume camp and are using one of the various prototype or batch PCB services try to avoid shops that ignore your fabrication drawing. A decent shop will look at and consider your drawing and give feedback if they cannot provide your requirements from their standard stackup selections.

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