# Synchronise SPI: options? Dedicated reset line? Series of reset bytes not allowed in data? Long break?

When using SPI, is there a common way of ensuring that when sending 8-bit words, that the sender and receiver know what is the start and end of a byte?

I'm guessing the best way is to assume that some period of no clock pulses from the master should be interpreted as a sort of reset, so the slave should assume any incomplete bytes/words should be abandoned, and the shift register reset? Is there some standard length accepted as a reset, either in multiples of some clock frequency, or some absolute time period?

• Most (all)? dedicated SPI controllers only run the clock during data transfer. Why can that not synchronise you? – Peter Smith Jul 4 '16 at 16:03
• Have you examined how your devices treat the select signal? – Ignacio Vazquez-Abrams Jul 4 '16 at 16:16
• The chip-select/slave-select pin is pretty much always used for this purpose. – Tom Carpenter Jul 4 '16 at 16:51
• @Mark With the SS (or CS) line. The devices I've used required the master to pull SS high, shift data, then pull SS low for a certain time, during which the contents of the shift register would be interpreted as a command and replaced with the result (which could be shifted out by pulling SS high again). – immibis Jul 5 '16 at 0:32
• @Mark "If SS is de-asserted prematurely" then what happens for any other hold time violation? You get unpredictable behaviour. "If a device doesn't clear its bit counter on SS" doesn't make sense because the devices do not have bit counters. "Or if the master starts transferring when the slave is not yet ready?" - the slave is always ready to transfer data when SS is high unless you have a hold time violation. – immibis Jul 5 '16 at 0:49

The SPI master and slave sync based on the slave select signal. They should stay synced by always counting the bits in lock step after the initial slave select.