Hello I have built a d latch using 4 NAND gates and an inverter made from transistors. Here is the schematic. D latch basic schematic http://courses.cs.tamu.edu/cpsc321/walker/labs/lab6.h6.gif

For some reason the latch does not remember its previous input like it is suppose to do. It just goes back to 0 as soon as I release the enable/clock button. I am using a 5v DC power source. Here is the truth table

Truth Table When I press data button and clock button I get a one but that one is not remembered. It just goes back to 0. I have drawn a schematic of my transistor d latch below. The data and enable pins are either connected to ground or 5v depending on what data wants to be inputted or saved.


simulate this circuit – Schematic created using CircuitLab

The led's do flicker quite a bit when I touch wires if that is a symptom of anything. The trapeziums are NPN transistors that are collector, base, emitter from left to right. The grey rectangles are diodes and the orange ovals are resistors. the black dots are connection points. Sorry for the bad drawing, I am not an artist. How can I get the d latch to latch the last input and if you happen to know how to stop the LED's from flickering that's a bonus. Thanks -Jack.

  • 3
    \$\begingroup\$ There is a schematic button on the editor toolbar. Redraw you schematic with that. We can't tell what the transistor pins are in your diagram. Draw the positive rail on top and the negative rail on the bottom and logic flow from left to right. \$\endgroup\$ – Transistor Jul 4 '16 at 17:54
  • \$\begingroup\$ As it is drawn 'C' is level sensitive, not edge triggered, which is what is needed. Right now 'C' is = to J-K type FF. \$\endgroup\$ – user105652 Jul 4 '16 at 18:10
  • \$\begingroup\$ Your first transistor is dead the moment you power up- positive supply straight into base. As for the rest of the circuit I don't see how its remotely equivalent to the block diagram showing nand gates \$\endgroup\$ – JIm Dearden Jul 4 '16 at 18:15
  • \$\begingroup\$ I have updated the question with a better schematic please see above \$\endgroup\$ – user2279603 Jul 4 '16 at 18:44
  • \$\begingroup\$ @user2279603: A latch or a flip flop? The truth table labaled "D flip flop" is not the truth table of a flip-flop but of a latch (a latch is level sensitive; a FF is edge sensistive) \$\endgroup\$ – Curd Jul 4 '16 at 18:50


simulate this circuit – Schematic created using CircuitLab

Figure 1. Circuit copied from original post and components dragged around.

Problem 1: No base resistors on Q1, Q4 or Q5. They will either be destroyed or the power-supply will shut down.

| improve this answer | |
  • \$\begingroup\$ Thanks for redrawing this mess. They will either be destroyed or the power-supply will shut down. Unless you have a proper lab-supply set to a very low current limit (100 mA or less): assume that the components will be destroyed. \$\endgroup\$ – Bimpelrekkie Jul 5 '16 at 12:44
  • \$\begingroup\$ how much resistance should I put in? \$\endgroup\$ – user2279603 Jul 5 '16 at 23:52
  • \$\begingroup\$ (1) Look up how to make a single NAND gate, build one and get it working with an LED. (2) Then build and inverter and get that working with an LED. (3) Then try drawing your circuit for the full latch, laying it out in blocks that can be identified. (4) If you're still in difficulty then please edit your question to explain where you got this circuit or if you made it up. Then explain what you think each component is doing. For example, in this circuit D1, D2 and D3 are doing nothing. Why are they there? \$\endgroup\$ – Transistor Jul 6 '16 at 6:23

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.