Why does old PMOS/NMOS logic needed multiple voltages like +5, -5, and +12 volts? For example, old Intel 8080 processors, old DRAMs, e.t.c...

I'm interested in the causes on the physical/layout level. What was the purpose of these additional voltages?

Yes, this question is about stuff which was used 35 years ago.

up vote 12 down vote accepted
+500

The 8080 used nMOS-only technology (no CMOS = pMOS and nNMOS). When you use nMOS (or pMOS) devices only, you have a couple of choices to build a logic inverter cell (see chapter 6.6 in this document, my answer borrows heavily on this source):

  1. nMOS transistor and pull-up resistor. Simple, but not good on an IC because the resistor would take up a lot of space on the silicon.

  2. nMOS transistor and a second, saturated nMOS transistor in place of the pull-up resistor. Not bad, but the high-level output voltage will stay one threshold voltage VGS,th below the supply voltage. (Note: VGS,th is the voltage between a FET's gate and source that will just turn on the FET.)

  3. nMOS transistor and a second, non-saturated (= linear) transistor in place of the pull-up resistor. High-level output voltage will swing all the way to VDD, but this comes at the extra cost of an additional voltage VGG with VGG > VDD + VGS,th. This is the reason for the +12 V rail.

  4. nMOS transistor with a second, depletion-mode n type transistor in place of the load resistor. No additional supply rail needed, but the technology is more sophisticated because two differetly doped transistors need to be made on the same chip.

It seems that the 8080 uses option number 3.

The reason for the negative rail (-5 V) could be the bias needed for a cascode configuration. This would increase switching speed at the cost of an additional supply rail. I can only guess here because I have not found any sources telling me that the 8080 really uses cascode-connected stages. Covering the cascode would be another story; this configuration is used for linear amplifiers, logic switches, level-translators or power switches.

  • one threshold voltage below the supply voltage - One what? How much is one "threshold voltage"? – Kevin Vermeer Jan 5 '12 at 17:18
  • @KevinVermeer: If the minimum V(GS) required to make an NFET conduct is, say, 2 volts, and the highest gate voltage available was 5 volts, then the output's sourcing current would drop to nothing as the output voltage rose toward 3 volts (5V-2V). – supercat Jan 5 '12 at 19:21
  • I seee... It makes more sense now... But what is cascode configuration? Also, maybe -5V is to be connected to bulk to help with sodium(=mobile ionic) contamination? – BarsMonster Jan 5 '12 at 21:18
  • My guessing for the negative (-5 V) voltage is really very vague and I don't know for sure if the 8080 uses cascode switches or if the substrate is biased. What makes matters worse is that searches for "negative supply" and 8080 or logic turn up lots of hits where the term "negative" is used for common or ground. It's not really wrong, but it doesn't help on this case. – zebonaut Jan 7 '12 at 9:38

Here's an example of a "depletion-mode" NMOS NAND gate circuit I found on (German) Wikipedia:

NMOS NAND Gate - public domain image by Wikipedia user Biezl

The upper transistor is used in depletion mode to provide a load approximating a current source and balancing the rise and fall times. Due to the higher threshold voltages of early MOS technology, a 12 V supply may have been needed to provide a proper bias for the gate of the load resistor. The -5 V supply might have been used to bias the back-gates (or substrate nodes) of all the FETs in order to get them in the desired operating regime.

I'm making this a Wiki answer because some of what I've said is speculation rather than hard facts and I'm sure someone here can improve or correct me.

  • For what it's worth, the video chip of the Atari 2600 runs mostly off +5, but has one input which is driven with a pot connected to the 9V supply. That input drives the gates of enhancement mode pull-ups in a sequence of 30 inverters whose average propagation time should be roughly 10ns (pretty fast by the standards of the day, I would think; no other signal has to propagate through anywhere near that many gates during a clock cycle). – supercat Jan 4 '12 at 20:32
  • Another comment re the enhancement-mode pull-ups: the ideal practical pull-up device in NMOS logic would be a constant-current source whose current-carrying capacity did not fall off as the output voltage increased. Unfortunately, if a FET gate is at five volts, VGS will drop by half by the time the source has reached 2.5 volts. By contrast, if the gate is at 12 volts, the output can reach 4 volts while VGS is still 2/3 what it was when the output was at ground. – supercat Jan 4 '12 at 22:47

I designed for 12 volt NMOS technology some years ago. It uses saturated n-channel transistors for the pull-ups. As described by a previous contributor (List item #2 in this answer), this limits the output voltage to one Vt lower than VDD. The 5 volt supply is used for interfacing with TTL. The -5V supply is used to bias the substrate and bring the Vt to a useful value. Without the bias voltage the Vt is about 0V.

  • +1, I hadn't thought of this exact reason for using +12V (for the internal logic) and +5 (for interfacing the internal +12-Vt H levels to clean +5V TTL H levels). – zebonaut Sep 23 '13 at 10:35
  • Do you know why Vt was so low without bias? Is that due to contamination issues? (Alkali metals and such) – BarsMonster Oct 2 '13 at 4:09

The short answer is, you need to study the circuit layout of a suitable device to see the design, and from this you can possibly work out why.

My gut feeling is that the design calls for interfacing with 5v TTL, but the device itself wont function at this voltage, exactly how it does function requires a suitable example to study.

This is easier said than done, as I can find very few details on the web.

What I did find was a wealth of info about the 8008, which predates the 8080 by a couple of years, this information includes ... a partial schematic, which you can find here.

http://www.8008chron.com/Intel_MSC-8_April_1975.pdf

Take a look round about page 29 and 30 (these are the page numbers of the pdf, not the hand scanned manual) and even page 5 if you want to see how it is physically constructed.

You can find more info here.

http://www.8008chron.com/intellecMDS_schematic.pdf

I don't expect any bounty for this, as I haven't directly answered the question, but I hope it points you down the correct path.

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