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It is often recommended to use multiple capacitors in parallel in bypass and decoupling applications, especially when working with frequencies above 50MHz.

There is some argument whether its better to use several of the same value capacitors or use capacitors of different values. Aside from that, is there any negative impact of placing the capacitors as close as possible to each other and the IC? Or should there be "some" trace between the capacitors?

Assume capacitor size are all 0603 or 0805. Is it better to place the capacitors side by side, or some alternate arrangement that leaves more trace between the capacitors?

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Yes, but not necessarily. They should be placed as close as possible to the voltage input pin they are decoupling. The aim of this is to reduce parasitic ESR and inductance. Dave from EEVBlog does a great job explaining decoupling caps.

"EEVblog #859 - Bypass Capacitor Tutorial"

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Yes indeed! I once had a huge 1.4 MHz spike which stemmed from a 47 uF electrolytic capacitor for energy hold-up in parallel with 100 nF for low impedance at 100 kHz switching, separated by total of 50 mm traces. That inductance formed a neat resonant tank which could only be removed by a new layout. If your routing is very low inductance, physical separation per se isn't harmful. Calculate your stray inductances, insert into spice and excite the system and you can see this with your own eyes.

In other cases you might have to do the opposite, have enough inductance to push the resonance to a frequency low enough not to cause any harm.

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