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Everyone knows that a CMOS inverter is simply a PMOS connected to an NMOS. There are situations in asynchronous design that we need to compensate for the inverter propagation delay in a parallel signal running along side of the other signal. In that case I can see that designers add a buffer in gate level schematics.

But I need to implement that buffer by myself using CMOS cell libraries and it seems to me the most rational approach is just to put two inverters in series which inverts the signal twice hence acts like a buffer. But it seems to me that the propagation delay also will be doubled.

How one can have a buffer with EXACT same propagation delay of an inverter?

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  • \$\begingroup\$ Can't you just feed your inverted and non-inverted signals to D flip flops (DFF's)? The flip-flop outputs should be pretty closely synchronized. Or maybe use a DFF cell library with complimentary outputs. I have never designed a chip. But if I needed to synchronize two signals in an FPGA that is what I would do. \$\endgroup\$ – mkeith Jul 6 '16 at 4:43
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    \$\begingroup\$ There is no clock in asynchronous circuits. \$\endgroup\$ – Ehsan Jul 6 '16 at 4:45
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    \$\begingroup\$ @mkeith: oh! you asked me a question which actually helped me to get the right answer! The answer to your question is that it depends on transistor length and width. But then realizing that I can see a solution: Choose small transistors for a buffer and a larger one for a single inverter. In that case propagation delay will be the same. \$\endgroup\$ – Ehsan Jul 6 '16 at 4:51
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    \$\begingroup\$ @Ehsan, it would be really helpful if you write up your answer at some point and answer your own question here. That is perfectly legal and desirable, and will make the site better for other people who come later. You don't have to give away any proprietary detail, but just a little bit more to help out the next person. \$\endgroup\$ – mkeith Jul 6 '16 at 4:53
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    \$\begingroup\$ Caution: getting exactly the same delay through sizing is harder than it sounds. Rise and fall delays are different. Delay is dependent on temperature and output load. This is why asynchronous design tends to use different structures like the Muller C-element. \$\endgroup\$ – pjc50 Jul 6 '16 at 13:25
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A common solution is to have to two path as shown in the figure below. The first path is a inverter chain to buffer the signal, or it could be a single inverter if the load is low. The second path is almost identical to first, but one inverter is replaced by a transmission gate like structure.

Using a simulator is should be possible to equalize the delays.

(Please note that the bulk should be tied to ground and vdd for the NMOS and PMOS, respectively. It's not drawn correctly.)

schematic

simulate this circuit – Schematic created using CircuitLab

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    \$\begingroup\$ If fiddling with the device characteristics is necessary to get the delays matched exactly, is it possible to just build a really slow inverter to match the upper pair? \$\endgroup\$ – Austin Jul 6 '16 at 9:38
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    \$\begingroup\$ Of course there are different ways to achieve the same result. Scaling an inverter could work as well. \$\endgroup\$ – Mario Jul 6 '16 at 9:56
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    \$\begingroup\$ I simulated the above circuit, there is still about 85ps mismatch. Measured at 50% signal level. \$\endgroup\$ – Ehsan Jul 16 '16 at 3:36
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I would suggest an exclusive-or gate. If you tie one input high, you have an inverter. If you tie one input low, you have a buffer. The propagation time should be the same.

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  • \$\begingroup\$ I don't know enough about the innards to know if the answer is correct but +1 for the idea! \$\endgroup\$ – Transistor Jul 6 '16 at 12:10
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    \$\begingroup\$ Not CMOS but the good old TTL data book has two tables of propagation delays (Tplh, Tphl), one for "other input high", the other for "other input low". Values differ by about 20-30% so, at least in TTL, not quite the same. So, use with caution. \$\endgroup\$ – Brian Drummond Jul 6 '16 at 13:12
  • \$\begingroup\$ This idea is cool, but it is inefficient due to the fact that the xor uses 8 transistors. @Mario's answer is actually the same as your answer. I think the most efficient way is to scale up the inverter in transistor level. \$\endgroup\$ – Ehsan Jul 6 '16 at 13:50
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One approach is to generate both buffered and inverted signals via the same stage, and there are two classic analog approaches to the problem.

I'll not translate them into CMOS, as I have no expertise at or below the cell library level. They may require matched stages for voltage level conversion before or after the stage itself.

The first is the classic phase splitter: based on a common source amplifier, its gain is approximately -R1/R2, or -1 with equal value resistors. (Component values are otherwise nonsensical). In this form it clearly isn't CMOS, though matched active loads would substitute for the resistors. One drawback is that its maximum voltage swing is only half the supply rail, and the DC level on each output is different.

schematic

simulate this circuit – Schematic created using CircuitLab

The second is the long tailed pair, which steers current from one leg to the other. Same remarks apply to replacing resistors with active loads, and nonsensical component values.

I am not convinced it will achieve such good balance of propagation delays, but at least the outputs can be at the same voltage levels and are not limited to half the supply.

schematic

simulate this circuit

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  • \$\begingroup\$ I think your first sentence may be the best suggestion here. E.g. if the signal is generated by an AND gate, you could replicate it with a NAND gate tied to the same inputs and that should (AFAICS) have the same propogation delay. \$\endgroup\$ – Jules Jul 23 '16 at 13:43
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    \$\begingroup\$ NAND is usually faster than AND, whose implementation is usually a NAND followed by an inverter. \$\endgroup\$ – Brian Drummond Jul 23 '16 at 18:25

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