I am currently reading Practical Electronics for inventors and am having a bit of trouble understanding the output of the following circuit: enter image description here

Now as I understand, if Vin>Vref then the transistor should be switched on and conducting therefore Vout should be equal to zero. But here it is indicated as +5V

Would be great if someone could clarify.Thanks

  • \$\begingroup\$ You need to understand opamp to figure out how comparators work. When Vin(noninverting input) is bigger than Vref(inverting input) it is normal for Vout to be Vs(5V). Transistor is just symbolizing the OpAmp's output. It is ON when Vin < Vref. \$\endgroup\$
    – Alper91
    Jul 7, 2016 at 5:46
  • \$\begingroup\$ What Alper91 says and if you just ignore that transistor, it does make sense. So the comparator's output is not the base of the transistor (like in your explanation) but the collector of the transistor. The transistor is there to show that it is an "open collector" type output and it can only pull the output down (not up). \$\endgroup\$ Jul 7, 2016 at 6:18
  • 2
    \$\begingroup\$ What I don't understand is that, in the example shown, the output is missing a small pulse after the larger one. \$\endgroup\$
    – dim
    Jul 7, 2016 at 9:33

1 Answer 1



simulate this circuit – Schematic created using CircuitLab

Figure 1. A standard inverting common-emitter transistor amplifier. This is not what the LT1011 symbol is depicting.

You are confusing the output of the comparitor with the inverting common emitter amplifier which does invert. The comparitor schematic symbol and operation is the same as that of the opamp and the output goes high when \$ V_+ > V_- \$ - i.e., the transistor turns off.

In this case the transistor symbol is added as a reminder to the use that the output is open-collector and that a pull-up is required for that reason. A look at the datasheet confirms that.

enter image description here

The open-collector output gives flexibility in, for example, ORing the outputs of multiple comparitors as shown in the Window Detector example. (The output will be pulled low if \$ V_{IN} > HL\$ OR \$ V_{IN} < LL \$.)

enter image description here

The datasheet goes on to explain the output stage as follows. Note the rather unusual feature (in Figure 5) that the emitter of Q2 has its own output pin so that the load can be pulled to a voltage other than \$ V^- \$.

In the “off” state, I1 is switched off and both Q1 and Q2 turn off. The collector of Q2 can be now held at any voltage above V– without conducting current, including voltages above the positive supply level. Maximum voltage above V– is 50V for the LT1011M and 40V for the LT1011C/I. The emitter can be held at any voltage between V+ and V– as long as it is negative with respect to the collector.

In the “on” state, I1 is connected, turning on Q1 and Q2. Diodes D1 and D2 prevent deep saturation of Q 2 to improve speed and also limit the drive current of Q1. The R1/R2 divider sets the saturation voltage of Q2 and provides turn- off drive. Either the collector or emitter pin can be held at a voltage between V+ and V–. This allows the remaining pin to drive the load. In typical applications, the emitter is connected to V– or ground and the collector drives a load tied to V+ or a separate positive supply.


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