# Significance of bias when driving an LCD

I've got hold of several bare-glass T218010 LCDs and would like to drive them with a bare MCU (or, rather, an MCU plus a couple latched-output SIPO shift registers such as 74HC595). However, the only useful information I've found on the topic of driving glass-only LCDs is Atmel app-note AVR340, which describes a way of driving a 1/2-bias 4-backplane LCD with logic-level output. The problem with this is that the particular LCDs I happen to have are stated in the datasheet to be 1/3-bias, and I haven't found any useful information on direct-driving those (besides the obvious "buy a driver IC"). Which led me to wonder how big of a problem it really is.

My question, thus, is how significant sticking to the datasheet-specified driving method is and what might happen if one were to violate the specs in that respect. On top of that, any additional knowledge on LCDs, methods of driving them, pointers to useful materials, etc. would be greatly appreciated.

• You need to provide the bias as dictated else there'll be a non-zero mean voltage across the segments which will result in permanent damage to the display after a while. Jul 7 '16 at 12:23
• Have you had a chance to look at the ATmega329 et alia yet? Jul 7 '16 at 12:25
• Have you referenced the signal levels of 1/2 and 1/3 bias LCD drivers themselves? What complexity does it take to replicate those with other devices? Jul 7 '16 at 13:54
• @TisteAndii If I'm not mistaken, the bias fraction refers to the fraction of VCC that the backplane levels are multiples of. i.e. 1/2 bias means that you drive the LCD in steps of 1/2VCC, with levels of 0, 1/2 and 1; 1/3 bias driving uses levels 0, 1/3, 2/3 and 1. In every case the DC component must be less than about 50 mV, which is way smaller than one third of a typical 3-5V supply. It is negated in all driving modes by also driving the segments in waveforms as to bring the average difference close to zero. Jul 7 '16 at 19:58
• @user2943160 replicating the signals would require me to organize an analog output with corresponding number of logic levels. For 1/2 bias it is quite easy to do by adding a high-resistance 1/2VCC voltage divider, grounding the pin for 0, driving it HIGH for 1×VCC and putting it into Hi-Z(input) state for 1/2×VCC (letting the divider take over). For 1/3 bias I'd have to use two pins for each backplane (for an additional 4 GPIO pins) and, possibly, organize a similar arrangement for all the segment pins (thus, 15 more pins and 30 more resistors). Jul 7 '16 at 20:05