I am using a Xilinx FPGA from the Kintek-7 family. The documentation for the memory resources can be found here.
Here are some important excerpts from the document (referencing pages 11 and 12):
The block RAM in Xilinx® 7 series FPGAs stores up to 36 Kbits of data and can be configured as either two independent 18 Kb RAMs, or one 36 Kb RAM. Each 36 Kb block RAM can be configured as a 64K x 1 (when cascaded with an adjacent 36 Kb block RAM), 32K x 1, 16K x 2, 8K x 4, 4K x 9, 2K x 18, 1K x 36, or 512 x 72 in simple dual-port mode. Each 18 Kb block RAM can be configured as a 16K x 1, 8K x 2, 4K x 4, 2K x 9, 1K x 18 or 512 x 36 in simple dual-port mode.
Each 36Kb block RAM can be set to simple dual-port (SDP) mode, doubling data width of the block RAM to 72 bits. The 18Kb block RAM can also be set to simple dual-port mode, doubling data width to 36 bits. Simple dual-port mode is defined as having one read-only port and one write-only port with independent clocks.
From this, I interpret that the data width of the BRAM is in multiples of 18. So it is 36 with dual port, or it could be 72 if you double that.
In my implementation I only need a data width of 64 bits. What happens to this extra 8 bits? Does it mean that I will not be utilizing the entire BRAM block?
Here is a graphic to help understand the way that I'm thinking: