tvalid delay in AXIS

Question

I am trying to feed the cosine wave from the DDS compiler to the multiplier and multiply with another cosine wave. The output of the multiplier is then feed into a CIC compiler as shown below.

I have directly wire the tvalid of the dds compiler to the cic compiler (bypassing the multiplier) since tvalid has to be '1' in order for the transfer to be initiate. The multiplier has introduce some delay and caused the output of the CIC compiler to be act like this: The sudden drop of output data at the beginning of the startup/ every time I change the phase of the cosine wave (it takes 4 times output sampling period) to be stable.

However, if I eliminate the multiplier, the sudden drop in output doesn't exist so I am guessing it is the multiplier delay.

I have tried the AXIS FIFO with asynchronous clock and also just wiring the tvalid of cic compiler to constant 1. The output is the same.

How can I delay the tvalid so that tvalid is rise to 1 only after the multiplication complete? Thank you!

Answer 1

You need to feed tvalid through a chain of FFs that are clocked by the same clock that the multiplier uses. The number of FFs needs to match the number of pipeline registers inside the multiplier — probably 2, but verify this.