I am trying to design a simple 1:2 demultiplexer. I have two question here. First, is the following design right?: (simulation shows that it is working)

in_D is the input data line, in_S is the selector and out_A and out_B are the two demux outputs.

enter image description here

I am currently using NMOS. Now the second question is: "Will it be better to use PMOS?" Or even a maybe a third question: "What is the conventional way to design a CMOS demultiplexer"?

Update: (Removing inverter and changing M2 to PMOS)

This actually worked but I am not sure if it can be used iin real design. Simulation is ok.

Removing inverter and changing M2 to PMOS

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    \$\begingroup\$ CMOS analogue switches (and multiplexers) use a CMOS pair for each switch normally. See analog.com/media/en/training-seminars/tutorials/MT-088.pdf Are you in a digital or analogue world? \$\endgroup\$ – Peter Smith Jul 8 '16 at 10:58
  • \$\begingroup\$ So I just need to get rid of the inverter and replace the bottom transistor with a PMOS? Looks so simple to be true. \$\endgroup\$ – Ehsan Jul 8 '16 at 11:07
  • \$\begingroup\$ No, you keep the inverter and you add a PMOS in parallel with each NMOS switch. In the schematic as it is now a 1 at in_D will not be transferred to the outputs. \$\endgroup\$ – Bimpelrekkie Jul 8 '16 at 11:24
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    \$\begingroup\$ It can work but it depends on the surrounding circuit (which you have not drawn) and what you're trying to achieve. But the one in my answer is more universal and will "always" work. \$\endgroup\$ – Bimpelrekkie Jul 8 '16 at 11:36
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    \$\begingroup\$ I would expect that this is the way in which they are implemented on 99.9999% of the ICs which use (de)multiplexers. So you would be in good company when using such an NMOS+PMOS passgate :-) When I need a (de)mux I always make them like this even when I know I could get away with only an NMOS. \$\endgroup\$ – Bimpelrekkie Jul 8 '16 at 11:42

This is a passgate or a transmission gate:

enter image description here

  • Take 2 of these

  • connect UA of both and use as input

  • The two UB will be the outputs

  • You can share one inverter between the two passgates (the input signal ST is the same for both).

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  • \$\begingroup\$ Alright thanks. Can you elaborate a bit what is wrong with my updated circuit which uses only one NMOS and one PMOS and no inverter? \$\endgroup\$ – Ehsan Jul 8 '16 at 11:35
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    \$\begingroup\$ The NMOS are needed to connect in and outputs when the input voltage is LOW, the PMOS are needed to connect in and outputs when the input voltage is HIGH. If in your case only a current only needs to flow only when the input voltage is LOW an NMOS only solution will work. \$\endgroup\$ – Bimpelrekkie Jul 8 '16 at 11:38
  • \$\begingroup\$ Beat me to it :) \$\endgroup\$ – Peter Smith Jul 8 '16 at 11:45
  • \$\begingroup\$ You win some you loose some :-) \$\endgroup\$ – Bimpelrekkie Jul 8 '16 at 11:47
  • \$\begingroup\$ I am the real winner. I got the right answer. lol \$\endgroup\$ – Ehsan Jul 8 '16 at 15:22

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