The altera DE2-115 board user manual section 4.8 page 47 describes the GPIO expansion header. It is clear that it has 3.3V and 5V power supply.

However, it later says that "The voltage level of the I/O pins on the expansion headers can be adjusted to 3.3V, 2.5V, 1.8V, or 1.5V using JP6 (The default value is 3.3V, see Figure 4-17)."

(1) I am confused, why is 5V power supply provided if no IO standard goes upto that? Also, why have IO standard down to 1.5V when power supply provided only goes downto 3.3V? Certainly an IC that takes 3.3V won't work with IO of 1.5V. Am I missing something here?

(2) Even though there are clamp diodes on these pins of the expansion header, is it ok to use a 5V IC that shall have VOH(max) of close of 5V?

  1. The FPGA doesn't use 5V, but some of the other parts on the board might. (The HD44780 LCD they're using often requires 5V on VCC, for instance.) Since it's there, they might as well provide it on the expansion connector in case you find it useful.

  2. Absolutely not. The clamp diodes are a last resort, and are only intended to protect the FPGA from brief overvoltage. Connecting a 5V output directly to a FPGA pin will cause a large current to flow through the protection diode, destroying it.

    Some development boards I've seen use small (e.g, 100Ω) series resistors on FPGA I/Os to limit the current through protection diodes. This limits the speed of these I/Os, though, and I would not recommend that you rely on this for large level shifts, like 5V to 3.3V.

    Bottom line: if you need to interface a 5V-only part to an FPGA, use a real level shifter. A 74LVC245, for example.

  • \$\begingroup\$ I understand that you presented 74LVC245 as an example only. However, I have looked into logic level translators before. What is the point of having logic level translation only in 1 direction i.e 5V to 3.3V and not the other way around (via step up of voltage 3.3V to 5V) as the 74LVC245 does? \$\endgroup\$
    – quantum231
    Jul 9 '16 at 22:12
  • \$\begingroup\$ @quantum231 The direction is switchable using the DIR input. \$\endgroup\$
    – user39382
    Jul 10 '16 at 8:00
  • \$\begingroup\$ yes but any IC of that type does not allow simultaneous 2 way communication like needed for SPI for example and for a 2 wire SPI I may need 2 seperate ICs. \$\endgroup\$
    – quantum231
    Jul 10 '16 at 22:18
  • \$\begingroup\$ Correct, but there are other parts that may be more appropriate if that's all you need. (Also, in my experience, SPI is more common at 3.3V than 5V.) \$\endgroup\$
    – user39382
    Jul 11 '16 at 5:31
  • \$\begingroup\$ "Some development boards ... use small (e.g, 100Ω) series resistors .... This limits the speed of these I/Os" -- this is probably why I've in the past had to use a buffer between an FPGA development board and an LED display using TLC59xx shift registers, despite the fact that the FPGA's output specifications easily exceeded what was specified by the shift register's datasheet to achieve maximum speed. It can be very confusing when you think you have a direct connection between two components, and then find that the module you're using interferes with that... \$\endgroup\$
    – Jules
    Jul 12 '16 at 7:45

Level shifters.

If you want to run a circuit at 5V, you can use the 5V line for power to your circuit. You then use the 3.3V and 5V to power level shifters to interface with the GPIO pins.

If you want to run your circuit at 1.5V or 1.8V (for example high speed memories typically have those levels), you can simply use a regulator to get the power supply for the circuit, and then set the I/O standard to 1.5V or 1.8V.

If you want to use a 3.3V device, then select the 3.3V logic levels! Just because you can select a lower voltage like 1.5V, doesn't mean you should. The choice is there to match the I/O voltage to whatever circuit you have attached.

Finally, no, it is not OK to connect a 5V output from a circuit directly to the FPGA pin, you must use a level shifter. If you do not, you will fry the I/O pin clamp diode and then the I/O pin itself.

This information can be found in the Cyclone IV Datasheet on page 12. In Table 1-15 it clearly states the maximum input voltage (Vih max) is 3.6V for the 3.3V I/O standard.


Further answer to point (1) beyond Tom Carpenter's answer: to run other devices, not necessarily interfacing with the FPGA digital I/O. I have worked with a custom-design expansion board for the 2x 40-pin GPIO connectors from Terasic products using Altera FPGAs where all of the digital signals were 3.3V, but some of the peripherals and other devices used +5V. These included the ADC and DAC (3.3V digital I/O, +5V analog side), a voltage reference, and the op-amp circuits for signal processing.

If necessary, the +5V could even be used to create a "clean" 3.3V or other voltage supply for devices on the expansion board.

For (2), the answer is mostly no. However, it is still possible to interface to 5V logic, with the correct protection and additional circuitry. When not able to use, as preferred, a level shifting IC, consider these older Altera app notes:

However, these app notes grow less applicable as I/O technology interfaces increase in speed and decrease in voltage compatibility. Whenever possible, try to use logic shifters.

  • \$\begingroup\$ Does using logic level shifter mean that I cannot obtain the maximum io frequency that the fpga is capable of? \$\endgroup\$
    – quantum231
    Jul 9 '16 at 9:43
  • \$\begingroup\$ @quantum231 depends on the choice of level shifter. Since the 40-pin GPIO interface isn't intended for high speed signals, the connector and layout will probably constrain your signal speed. You would want to ask another EE.SE question to discuss level shifter choice. \$\endgroup\$ Jul 9 '16 at 15:14

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