# Metastability simulation

I am trying to observe the metastability by simulating (LTSpice) a chain of inverters and probe the signals in between.

The oscillation never happens (I put more than 5 inverters to ensure enough propagation delay.) The signal just stay at 50% of VDD.

The moment that I change another unconnected signal (to the inverter chain) the chain of invrters starts to oscillate but it never shows any metastability and it always starts from 0 then 1 then 0 and so on. I expect that the initial point sometimes starts from 0 and sometimes from 1, but I does not.

How can I simulate a circuit with real metastability in place?

• You're describing a ring oscilator circuit, but using the terminology appropriate to sequential logic. Commented Jul 9, 2016 at 8:21

Metastability is generally not oscillation, but the signal from a latch, not an inverter, hovering around 50% of rail for an extended period of time before settling to one or other state.

Just a few weeks ago, I successfully observed metastability in an LtSpice simulation. I googled for a transistor level model of a d-latch, and then used a binary search for the exact input voltage that would make it metastable.

If you look carefully at the latch, you'll see it is a pair of inverters 'hugging each other', with two transmission gates, one to break/enable their feedback loop, the other to connect an input signal in, driven by anti-phase clock signals.

You need those transmission gates, or at least something like it, to set the initial conditions required to get the inverters into the metastability region. As an alternative, you could simply use a pair of inverters, with a low value capacitor to one node, say 1fF, and set the cap's initial conditions parameter to force the initial voltage. However, doing it with transmission gates like this is more realistic, it's what is actually inside a d-latch.

These FET models I found are from a very fast process, hence the low voltage. The normal propagation delay was around 50pS, here you can see the delay has increased to around 600pS, with an extended flat portion before the flop decides which way to settle. I couldn't get it any longer, as I've run out of precision for setting the initial voltage, and LtSpice internally probably only uses double precision.

The models were downloaded from CMOSedu.com, though I can't find the latch model yet, the cmosedu_models.txt should be easier to find. I can post my .asc file if you like and if that's possible.

• Thanks. Actually metastability can occur anywhere, even when two cute inverters hugging each other in 69 position :-) look at this post: electronics.stackexchange.com/questions/14816/… Commented Jul 9, 2016 at 7:16
• My goal is not to observe the metastability, I am just wondering why it does not happen in my chain of inverters. Commented Jul 9, 2016 at 7:22
• @Ehsan You are right, a pair of inverters could exhibit metastability. But, how do you set up the initial conditions just right, and then allow them to demonstrate it? The easiest way I can think of is to use a transmission gate to break the feedback path, and use another transmission gate to bias them to some intermediate voltage. Then at some point, switch the gates over. Viola, you've built a transparent d-latch. Examine the circuit I have posted above and you'll that that's exactly what's there. Commented Jul 9, 2016 at 7:41
• @Ehsan So, what is wrong with your inverter circuit for setting them up to demonstrate metastability? I don't know. Post a screenshot of the circuit you are using, and let's have a look. It's all in the details. Commented Jul 9, 2016 at 7:42

It may happen that you are observing genuine numerical metastability in your ring oscillator simulation. As the metastable state is the state of unstable equilibrium, two inverters with the outputs of each one connected to the inputs of another one has a metastable state, the voltages of which can be calculated from a voltage transfer characteristic. It is the point where $$\V_{out} = V_{in}\$$. Because the $$\V_{out}(V_{in})\$$ is a continuous monotonic function with $$\\text{maxval}(V_{out})=\text{maxval}(V_{in}),\,\text{minval}(V_{out})=\text{minval}(V_{in})\$$ (almost true for CMOS), this point always exists. If the two inverters are identical, the voltages at inputs and outputs are equal, and if you have five identical inverters connected in a circle (ring oscillator), this circuit also have a metastable state with input/output voltages equal to those of the metastable state of the pair of identical inverters.

When, prior to a transient analysis, the simulator computes operating point for a chain of (two or more) inverters connected in a circle, by the same token it also computes the voltages of the metastable state for this circuit. So, in theory, the ring oscillator should never oscillate with undisturbed initial conditions of operating point analysis. In practice, the precision of the calculation is finite, and, what matters more, the operating point is calculated with a precision only sufficient to launch a transient analysis: no need to waste the time for higher precision required for illusory goal of metastability observation; all the more so because this observation cannot be developed into a useful tool for circuit designers.

The numerical error of this .op calculation can lead to oscillations, but accidentally it can become small enough and the transient analysis can result in "frozen" voltages and currents of the circuit. I never heard this wording, but we can name this scenario a "numerical metastability", because it has much in common with genuine metastability.

We can use the simulator to calculate the $$\V_{out} = V_{in}\$$ point. Unfortunately, the .op analysis in LTspice gives only six decimal digits of voltages (V(inout)=V(wire1)=0.6198945), and this precision is not sufficient to demonstrate the "numerical metastability". But we can export the transient graphs to the text files, only do not forget to disable the waveform compression in the control panel. Notice also '.option numdgt=14' in the simulation.

The exported text file gives us a somewhat different values for input/output nodes, V(inout)=0.6198948233567885 and V(wire1)=0.6198948233566100. More alarming is the fact that the voltages at 3ns are V(inout)=0.6198948233611358 and V(wire1)=0.6198948233604235, so we run the simulation for a stop time of 10ns:

I'm not specifying a max timestep parameter deliberately; if unspecified, the simulator defines a greater value of this parameter for a 10ns analysis. Had the simulator-defined operating point be an exact "numerical metastability" voltage, the graph would be constant irrespective to the value of the time step.

So I accept a value of Vmeta=0.6198948233567 as an initial value and use a successive approximation method to define a more precise value for this parameter. Actually, I do it by trial and error. The value found is Vmeta=0.619894823357571. With this value, I run a .step param simulation for the just defined "numerical metastability" voltage and for a few voltages of a bit smaller and greater values. To do the plot more pronounced, the initial condition is modified only for the 'inout' node:

Now, back to the ring oscillator. All the graphs are of the V(inout) voltage; the colors vary for three different initial conditions, the exact Vmeta defined earlier for two 'hugging' inverters, a bit smaller value and a bit greater value. Notice how more components in the circuit require smaller timestep (0.05ps) for the simulation to demonstrate 'numerical metastability' at the earlier calculated Vmeta=0.619894823357571:

This simulation gives us an opportunity to see how the "numerical metastability" tells more about the simulator computation procedure than about a real metastability phenomenon. Change the max timestep to 0.025ps and the oscillations start in only one graph. Change the max timestep to 0.01ps, and the oscillations do not start at all. Smaller timesteps result in less perturbation, and the voltages restore their initial condition values at each next step.

In the hope that adding noise to simulation moves us closer to the "genuine metastability" simulation pictures, I add a behavioral voltage source of pseudorandom white noise to the circuit. This noise source does hardly ever simulate the real MOSFET noises, but the .tran plot is similar to those presented in EE course slides on metastability.

A zoomed-in region of the graph

Metastability with latches

Having simulated numerical metastability with a pair of inverters and a ring oscillator, it is quite natural to try and create the simulation with the latch. To force the inverter pair and oscillator circuits into a metastable state, we were adjusting the initial voltages. With latches, for the same purpose we have to set the delay between the data and the clock transitions to a certain predetermined value. When the clock pulse is cutting off the data line from the bistable loop (a pair of inverters "hugging each other" via the transmission gates in the latch), the inputs/outputs of these inverters are left with certain voltages. Sure, even in the metastable state these "autonomous" voltages change with time, but you can still reckon the latching moment as mapping the delay times to the "metastability" voltages. The essential difference is that in latches there exist multiple parameters which have to be consistently adjusted for creating the circuit metastability condition, although in practice the problem is solved by the same "successive approximation method", by trial and error.

So I capture a CMOS latch circuit in its most primitive form, as it is given in introductory digital design courses, and run a .step'ped-over-delay simulation:

The data are getting latched for clkdelay > 20p, so the next iteration is '.step param clkdelay 20p 30p 1p'

the data latched for delays > 25p, the next step '.step param clkdelay 25p 26p 100f', and we increase the stop time parameter to 100ps

and so on up to the tenth iteration, which gives us a metastable state at the delay of 25.647993107975ps (delay in the clock line) - 10ps (delay in the data line) = 15.647993107975ps. These metastable equilibrium lasts for more than 130ps, with the V(out) voltage of approx. 0.544V.

The process is straightforward, but tiresome and long: the timestep must be very small (one femtosecond here) to give a likeness of credibility to the simulation. Notice the very small iteration step ($$\10^{-22}\$$s) for the delay step in '.step param ...' of the last simulation. It may appear inconsistent with the simulation time step of one femtosecond, but it is not. To understand what happens here, consider the concept of the parameter (Vmeta or $$\\text{delay}_{meta}\$$) as roughly corresponding to the concept of Dedekind cuts in the theory of real numbers. Suppose you can solve exactly for the parametric curve (curve) of Vout, where the parameter is the delay between the data and the clock signal assertions, Δt. Then, if for all 0 < Δt < ΔTmeta the Vout ends up as a logic ZERO(ONE), and for all Δt satisfying ΔTmeta < Δt < ΔTperiod the Vout ends up as a logic ONE(ZERO), it is reasonable to define ΔTmeta as the delay value forcing the circuit into the metastable equilibrium. This definition can appear as excessive mathematization, but its usefulness becomes evident when we consider the finite precision of the simulation (finite max timestep). With numerical experiments you can prove for yourself that for a very small iteration parameter in '.step param ...' simulation the family of V(out) curves becomes unordered with respect to the delay: with the delay increasing, the final Vout can first switch from ZERO to ONE, then again to ZERO, and then again to ONE. This 'very small iteration parameter' value depends on the precision of the simulation, namely, the max timestep -- the smaller the timestep, the smaller this 'very small iteration parameter' should be, although the factor of proportionality (if these parameters are proportional) is not so obvious. For the simulations of the above pictures, where the max timestep is 1fs, this threshold for an iteration parameter of .step operator is $$\10^{-22}\$$. For iteration parameter values less than $$\10^{-22}\$$, the ordering of Δt-parametrized graphs in these 1fs-timestep simulations becomes broken. Because the max timestep parameter defines the simulation evolution from the beginning, the entire task of finding the simulation demonstrating the maximum metastability duration should be performed with a constant max timestep value -- you cannot decrease the max timestep after a certain successive approximation step and continue with the next step of your successive approximation method. Still, in order to increase the duration of the metastable equilibrium, we need to decrease both the timestep and the delay precision. I hope the pointlessness of these computations is evident now.

Quite naturally, the V(out) voltage is different with the value for a metastable equilibrium of the pair of inverters "hugging each other", because there are transmission gates in between the bistable pair inputs/outputs in the latch (not mentioning that I changed the transistor sizing for plotting convenience, and Vmeta for the pair 20n/20n 50n/20n Vdd=1.2 is now Vmeta=0.65697159553).

For reference, here is a plot of node voltages for this simulation: