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(Surplus story removed.)

I was explaining MOSFETs, CMOS, and logic gates to someone and realized I didn't grasp some concepts as well as I thought.

It culminated when he drew a single transistor, put the two inputs at the gate and source and the output at the drain, and said "Why isn't this an AND gate?"

I hesitated, then said that the truth table for that circuit would have Z (high impedance) as the output when the gate was 0 and the source is 1, and that's not an AND.

But then I realized that I don't understand Z very well. It's high impedance, meaning little/no current flows. But isn't that the same as the situation between two points at 0V?

So, my questions:

  1. If current is the flow of electrons, how do they traverse the positively charged channel in the n-type?
  2. In the p-type, the body has a lack of electrons anyway, so how does current flow when voltage isn't applied to the gate?
  3. How are 0V and Z different?
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    \$\begingroup\$ Great questions, but maybe too many? One thing that jumps out at me, when considering MOS transitors, is that they are voltage controlled devices, not current controlled. The voltage from gate to source is what determines the conductivity of the channel (from source to drain or drain to source). For now, think of the gate current as being zero. Sure there is some leakage, but to a first approximation, the gate current is zero, and more importantly, even if it is not zero, it is the voltage from gate to source that controls the channel. \$\endgroup\$ – mkeith Jul 9 '16 at 17:54
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    \$\begingroup\$ Concentrate on asking better questions and much, much less about the pointless back-story. You can make this question much more readable if you get rid of the surplus wordage. \$\endgroup\$ – Andy aka Jul 9 '16 at 18:00
  • \$\begingroup\$ Hence the name: FET: Field Effect Transistor… it's the electric field created by the gate to source voltage that controls current conduction. \$\endgroup\$ – AndyW Jul 9 '16 at 18:01
  • \$\begingroup\$ You've reversed the doping profile of the N-type FET. The body is doped with acceptor ions and is P-type. The source and drain contacts are embedded with donor ions and are N-type. In the P-type FET the body is N-type and the drain and source contacts are P-type. \$\endgroup\$ – Captainj2001 Jul 9 '16 at 18:05
  • \$\begingroup\$ This link has a pretty good basic description of JFET (depletion mode device) and N-MOSFET (enhancement mode) operation: learningaboutelectronics.com/Articles/N-Channel-MOSFETs \$\endgroup\$ – Captainj2001 Jul 9 '16 at 18:15
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If current is the flow of electrons, how do they traverse the positively charged channel in the n-type?

Refer to Fig. 1 below. In an N-type enhancement mode MOSFET, \$V_{gs}\$ establishes an electric field through the gate, the dielectric layer, and the P-type substrate. This electric field draws electrons up through the P-type substrate and "induces" an electron channel (an N-channel) under the dielectric layer. When VGS>Vth, the field strength is sufficient to induce (and sustain) under the dielectric an electron layer that stretches between the source and drain terminals, and if \$V_{DS}>0\$ the transistor starts conducting current between its drain and source terminals.

enter image description here

Figure 1. N-type enhancement mode MOSFET

As shown in Fig. 1, the substrate (B) is connected to the source (S), which is connected to the negative terminal of the power supply, which serves as the source of the electrons that are injected into the P-type substrate. In Fig. 2, the three vertical bars represent the drain, substrate (with the arrowhead), and source elements (top to bottom). Note that the substrate is internally connected to the source in both the N-type and P-type MOSFET.

enter image description here

Figure 2. Schematic symbols for enhancement mode MOSFETS

In the p-type, the body has a lack of electrons anyway, so how does current flow when voltage isn't applied to the gate?

Both the N-type and P-type enhancement mode MOSFETS are "normally off" devices; the transistor turns ON only when the condition VGS > Vth is satisfied. When VGS < Vth, the transistor is OFF (very high resistance between the drain and source terminals).

enter image description here

Figure 3. P-type enhancement mode MOSFET

Depletion mode FETs, on the other hand, are "normally ON" devices. A "Junction FET" (JFET) is an example of a depletion mode device. Consider the N-channel JFET in Fig. 4. When a \$V_{DS}>0\$, current immediately begins to flow through the device. A reverse bias voltage applied to the N-channel JFET's gate relative to its source (\$V_{GS}<0\$) creates an electric field that constricts the current-carrying drain-source channel—i.e., the field "depletes" the number of charge carriers in the current channel, thereby reducing the flow of current. With sufficient negative gate-source bias, the electric field strength completely "pinches off" the flow of current in the drain-source channel, and current flow drops to approximately zero amps.

enter image description here

Figure 4. Junction field effect transistors

How are 0V and Z different?

Voltage is potential difference. Given two different nodes within a circuit, nodes A and B, each node has its own electric potential (with units of Volts).

$$ V_{AB} = (potential @ A) - (potential @ B) $$

If \$V_{AB}=0\$, then \$potential@A = potential@B\$.

When designing a circuit, the circuit designer arbitrarily chooses one node—e.g., node B—to be the "reference potential" node, and all voltages (potential differences) in the circuit are measured relative to the reference node (which is often called the "ground" node). The potential at the selected reference node is specified as "zero volts" (0V) so that all other voltages in the circuit are a positive or negative offset from zero.

The high impedance, or "High Z", state refers to a condition within a complementary metal oxide semiconductor (CMOS) circuit where the P-type and N-type enhancement mode MOSFET pair are both turned OFF.

PMOS  NMOS  Q
-----------------------
OFF   OFF   HIGH Z
ON    OFF   LOGIC HIGH
OFF   ON    LOGIC LOW

In Fig. 5, when both the PMOS and NMOS transistors are OFF, there are very large resistances between the power supplies (VDD and VSS) and the output terminal Q. Consequently, approximately zero current flows into or out of terminal Q when the CMOS device is in its "high Z" state. Note that there could be a non-zero voltage at Q relative to the circuit's reference/ground node; however, in the high Z state the output impedance at Q is so high that there will be approximately zero amps flowing into or out of terminal Q.

enter image description here

Figure 5. CMOS circuit

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  1. If current is the flow of electrons,

It's not. Current is the flow of electric charge. It may be carried by electrons (or holes, or ions) but it is not the same as the movement of the electrons themselves.

how do they traverse the positively charged channel in the n-type?

It's not charged. The electric field created by the voltage on the Gate changes the resistance of the channel via Field Effect.

  1. In the p-type, the body has a lack of electrons anyway,

It's not exactly a lack of electrons, but spaces in the crystal lattice where electrons could fit. Without holes all the electrons would be bound to their atoms, so the crystal would be an insulator. The holes provide spaces that electrons can jump into, leaving other holes behind them which become the flow of current.

so how does current flow when voltage isn't applied to the gate?

In an enhancement mode MOSFET, current doesn't flow when the Gate to Source voltage is zero.

How are 0V and Z different?

0V is a logic level. 'Z' (high Z or high impedance) is an open circuit (OC). Since an open circuit takes whatever voltage is applied, a meter connected to Ground will show no difference between 0V and 'Z'. They can be distinguished by applying voltage through a pull-up resistor. An output which is actively held at 0V will stay at 0V, but an OC output will rise to the voltage at the other end of the resistor.

Open circuit outputs are useful for wired-AND circuits where several outputs may need to be wired to a single input, eg. the INT input on a CPU which senses multiple interrupt sources. It is also used for controlling access to a common bus, where one device at a time puts signals on the bus while the others are kept in high Z.

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  • \$\begingroup\$ If a meter connected to ground shows no difference between 0 and Z, does "Z" at the gate of a transistor behave the same as "0" -- just a "0" that's easily overridden? And if so, why doesn't the one-transistor AND gate I described work, assuming no other devices are applying a logic level to the connection? \$\endgroup\$ – user1274193 Jul 9 '16 at 22:41
  • \$\begingroup\$ High Z isn't a "0", it's nothing. Depending on the impedance of the following input it could be seen as 'high' (TTL), or floating between high and low (CMOS). One input on the Source and the other on the Gate isn't an AND gate because (assuming a pullup on the Drain) the output is "0" only when the Gate is a "1" and the Source is a "0". That's the same as a NAND or an OR with one inverted input. \$\endgroup\$ – Bruce Abbott Jul 9 '16 at 23:27

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