In these situations, contention is the name of the game. Specifically contention between the feedback inverter and the driving inverter.
However, in this case, there is a header and footer device, which prevents contention. This removes a lot of the timing restrictions for a functional circuit and makes the tuning nearly foolproof. To test this, push a few 1's and 0's through. Functionally it should work for any sizing. BUT, the sizing will have a large effect on the setup and hold times (metastable window), along with the clk->Q delay.
So lets take a look at the sizing in the original schematic.
The feedback inverter is made with M13/M14, whose W/L ~ 5
The feedforward inverter is made with M9/M10, whose W/L ~ 1.5
The header/footer is made with M5/M6, whose W/L ~ 5
The driver inverter is made with M1/M2, whose W/L ~ 2.5
In the circuits, the feedback and feedforward inverter are both in series with the header/footer FET's. So the equivalent W/L ratio for these is reduced.
Equivalent W/L for feedforward inverter when on: (1.5*5)/(1.5+5) = 1.15
Equivalent W/L for feedback inverter when on: (5*5)/(5+5) = 2.5
This is the same strength as the driving inverter (M1/M2).
So, I would just scale the values keeping the ratios the same. You can also incorporate the beta ratio into sizing the PMOS vs the NMOS. But, this will only effect the setup/hold/clk-q and is not necessary for functionality (again due to header and footer devices).
Of course simulate the circuit to check.
As another user mentioned you will want the clk and clkbar signals to be very well driven and with low delay b/w both pieces of this circuit. Otherwise they will fight to drive the output node Q during the clock overlap.
Check above reference for more topologies of DETDFF's.