Dual edge triggered D flip flip CMOS implementation. Less than 20 transistors

Question

I need to implement a dual edge triggered D flip flop (DET) in a CMOS IC using 0.35u technology. The best design which I could find is this one.

I attached the circuit to this post also.

First question is: As I am using 0.35u then is it enough just to scale the W/L ratio of the given design (it assumes 1u technology) or there other things to consider? The designer emphasizes that W and L are important and it will not work if we don't follow the given specs.

Second question: I implemented the design in that paper, but the given circuit just doesn't work right now. Is there another design which uses less than 20 transistors and can perform latch on both rising and falling edge of clk?

Answer 1

If I wanted to implement this on 0.35 um I'd just copy the W/L as they are in the paper and try to get it to work in the simulator.

The W of 4 or 8 um is most likely chosen to make the W = 8 twice as strong as the W = 4. The L = 2.6 devices must be weaker even than the 4/1.6 devices.

Normally I would expect PFETs to have 2 to 3 times the width of it's counterpart NFET, this is to compensate for the weaker PFETs. PFETs are always weaker because hole mobility is less than electron mobility. I do not see that 2 to 3 ratio here which I find odd.

Maybe to get the circuit working the PFETs need to have their W increased a factor 2 to 3.

Once the circuit is working I'd try to scale it down to minimum size L and W but keeping the W/L ratios.

You could take one huge step and scale everything down in one go but my experience tells me that most often this results in a design that doesn't work so you will have to get back to the original anyway and take small steps. So I do that right from the start ;-) and use the simulator a lot of course.

A quick search reveals that you need at least 20 transistors for this function so I think it doesn't get simpler than this.

Answer 2

In these situations, contention is the name of the game. Specifically contention between the feedback inverter and the driving inverter.

However, in this case, there is a header and footer device, which prevents contention. This removes a lot of the timing restrictions for a functional circuit and makes the tuning nearly foolproof. To test this, push a few 1's and 0's through. Functionally it should work for any sizing. BUT, the sizing will have a large effect on the setup and hold times (metastable window), along with the clk->Q delay.

So lets take a look at the sizing in the original schematic.

The feedback inverter is made with M13/M14, whose W/L ~ 5
The feedforward inverter is made with M9/M10, whose W/L ~ 1.5
The header/footer is made with M5/M6, whose W/L ~ 5
The driver inverter is made with M1/M2, whose W/L ~ 2.5

In the circuits, the feedback and feedforward inverter are both in series with the header/footer FET's. So the equivalent W/L ratio for these is reduced.

Equivalent W/L for feedforward inverter when on: (1.5*5)/(1.5+5) = 1.15
Equivalent W/L for feedback inverter when on: (5*5)/(5+5) = 2.5

This is the same strength as the driving inverter (M1/M2).
So, I would just scale the values keeping the ratios the same. You can also incorporate the beta ratio into sizing the PMOS vs the NMOS. But, this will only effect the setup/hold/clk-q and is not necessary for functionality (again due to header and footer devices).

Of course simulate the circuit to check.

As another user mentioned you will want the clk and clkbar signals to be very well driven and with low delay b/w both pieces of this circuit. Otherwise they will fight to drive the output node Q during the clock overlap.

https://ece.uwaterloo.ca/~cdr/pubs/wai_masc.pdf

Check above reference for more topologies of DETDFF's.