I am trying to look for a hardware solution to my current problem. Currently I am using an AFG preprogrammed with a signal (example below, 8bit resolution is OK, using 30 or more data points each 1us in duration). I would like to replace this AFG with an IC that I can program through SPI or similar. Then when I want a signal trigger it with TTL or equivalent.

I have found a few IC's that are similar to what I want, specifically a SPI DAC, with memory for one data point MCP4725.

Also I have found a few sweep programmable square and sine wave systems but not anything that can satisfy my needs.

I understand there may not be a solution, but I am hoping that it is just that I am using the wrong search terms.

Terms used;

"DAC with memory and frequency" "IC AFG" 'IC arbitrary function generator'

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  • \$\begingroup\$ Use a microcontroller? \$\endgroup\$
    – dim
    Jul 13 '16 at 7:30
  • \$\begingroup\$ There is a solution using a parallel load DAC with an external memory and clock. Once I have some free time (tomorrow probably) I will sketch it up. \$\endgroup\$ Jul 13 '16 at 13:00

Use either a microcontroller (if you're comfortable writing software) or an FPGA (if you're comfortable with VHDL/Verilog hardware design). Same basic idea either way:

Organize memory using phase from 0 to 360 degrees as the memory address, and store one or more complete waveforms in that space. The data should be scaled to fill the available dynamic range.

Designate a counter (wide enough to address the memory) as the "phase accumulator". This counter will run from 0 to 360 degrees. Use modulus arithmetic to handle overflow e.g. 355 degrees plus 10 degrees = 5 degrees.

Use a timebase (such as a clock oscillator or a timer tick interrupt) to periodically read the memory, at the location addressed by the phase accumulator. Scale the data before sending it to the DAC -- this is where you can add an offset or adjust the gain. Be sure to handle overrange/underrange saturation of the DAC codes.

After writing the DAC, increment the phase accumulator to point to the next sample. The output frequency depends on the phase increment and the frequency of the timebase.

For best results, ensure that each output cycle gets at least 10 points per cycle. Although 2 points per cycle is barely sufficient to avoid frequency aliasing (Nyquist limit), this condition also has 100% error in amplitude and phase, so is not really sufficient for signal reconstruction. At around 10 points, a reconstructed sine wave begins to resemble an actual sine wave.

I've never seen a single IC solution for arbitrary function generation. The DAC usually is just a DAC without any signal processing backend. I was involved in the design of the Maxim Integrated MAX5318 Evaluation Kit, which uses a Xilinx Spartan 3 FPGA to implement arbitrary function generation.

I think the reason you're not going to find an integrated DAC plus Arbitrary Function Generator all on one IC package, is because precision DAC is fairly expensive to design and test, while RAM is a commodity. Every year RAM designs get squeezed tighter and cheaper, while precision DAC solutions get designed into long-term industrial and ATE applications. In other words, the DAC customer base and RAM customer base pull in opposite directions. There's no economical way to integrate the two functions into a single IC. If you want to bankroll a custom IC project, I'm sure it could be technically feasible for some price. But I guarantee you're not going to like the price, especially at low volume.

  • \$\begingroup\$ Thank you for the detailed comment, and sorry for the late reply. I have used Arduino and Pic systems in the past, but i thought that they would be too slow to achieve a signal generation of 100ns per sample? \$\endgroup\$
    – CraigS
    Jul 17 '16 at 14:36
  • \$\begingroup\$ FPGA systems are an interesting solution. I have no experience with these, but they have a large number of outputs. To drive every channel with an 8bit DAC I would need 8x32 pins. The reason I was hoping for a storage/recall system was to free up pins on the FPGA/microcontroller. \$\endgroup\$
    – CraigS
    Jul 17 '16 at 14:37
  • \$\begingroup\$ I have been thinking of a system involving shift registers and a DAC, to drive the 8 bit DAC with only three outputs. Although I am not sure how quickly I could rewrite the register, this would have to be done within 1us I believe. \$\endgroup\$
    – CraigS
    Jul 17 '16 at 14:39
  • \$\begingroup\$ The way this has been done in past eras was to program the waveform into an EPROM or Flash chip as numeric values which are delivered one-by-one to the DAC. The memory chip then has its address lines driven sequentially by a binary counter IC (e.g. 74x160, 74x93). The 8-bit output of the memory chip drives the DAC inputs. Viola! Waveform on output of DAC. The tricky part is making the counter chips operate in a compatible modulo-n mode and choosing the appropriate counter clock frequency. Not a big deal if you are a good logic designer. Of course, you need a means of programing the memory chip \$\endgroup\$
    – FiddyOhm
    Oct 11 '16 at 11:56

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