I've looked at a couple of posts on this topic, but I can't really get a feel to them. Does the LUT have an input where the logic address is given, or does the LUT read from the D Latch? If anyone has a picture that describes this, it would be very helpful, since in most pictures I found online, all the logic cell pictures had a LUT with no inputs, which confused me since there was no way for it to read logic. Thank you for your help!

  • \$\begingroup\$ Welcome to EE.SE. What is a LUT? \$\endgroup\$
    – user105652
    Jul 15 '16 at 0:07
  • \$\begingroup\$ @Sparky256 Look-Up Table. In digital logic they map one or more inputs onto an output. \$\endgroup\$ Jul 15 '16 at 0:08
  • \$\begingroup\$ @TomCarpenter. OK. Something like LAB (Look-Aside-Buffer). We have so many acronyms on this site I was not sure. \$\endgroup\$
    – user105652
    Jul 15 '16 at 0:13
  • \$\begingroup\$ @Sparky256 different vendors call them different things. Although in some FPGAs "LAB" stands for "Logic Array Block". \$\endgroup\$ Jul 15 '16 at 0:15

A LUT (Lookup Table) in modern FPGAs is nothing more than a RAM. The inputs are the address lines, and the output is the data output bus. There's really nothing more to it.

FPGAs also tend to have more advanced logic modules (some vendors call them ALMs) which consist of one or more LUTs along with additional dedicated adders, high speed carry chains, and typically an optional register (flip-flop) on the output. The inputs connect to the logic routing resources in the FPGA (which are also typically just RAMs) and in some cases also have a feedback path to connect to the output register of the same ALM.

All of the LUTs are initialised at power on by a configuration file which essentially uses the write port of the LUT RAM to program it. Once configured the memory acts to perform whatever logic function it is programmed to do.

As @duskwuff reminded me in the comments, it is in many FPGAs possible to use the LUT as a RAM directly. In designs where this is the case, additional inputs to each LUT are made available which form the a write data port (typically this port is a single write data bit and a write enable bit, and the address is shared with the read port).

For a diagram of what the ALMs or ALUTs or LABs (or whatever a vendor calls them) look like for a given FPGA, you can typically find this in the documentation for the device family. Different FPGA families will have different structures.

As an example, here is the structure of an ALM (Adaptive Logic Module) for an Altera Cyclone V FPGA (taken from the datasheet on p20). I've added some annotations.

Cyclone V ALM Structure

The LUT is on the right, then there are some dedicated full-adder (FA) blocks which allow high-speed multi-bit adders to be made by chaining multiple ALMs together (using the dedicated carry chain routing). Then a multiplexer to select whether or not the FA should be used, and finally the output registers.

There are lots of other signals like clocks and resets for the registers and the configuration interface for the LUT which are usually not shown on the diagrams for simplicity, but they are there.

  • \$\begingroup\$ Thanks, this actually helped a lot! So, if the LUT is a memory module that does the logic, why do FPGA logic cells have an optional register and a 2 to 1 multiplexer? \$\endgroup\$
    – Techie
    Jul 14 '16 at 23:17
  • \$\begingroup\$ @Techie the LUTs don't have any clocked registers in them (they are SRAM) which allows them to be used as combinational or asynchronous logic. The output register allows the LUTs to then be used as synchronous logic. The various multiplexers shown in the diagrams are typically there to give you an idea of what can connect where - in practice they will all be part of the memory. \$\endgroup\$ Jul 14 '16 at 23:37
  • \$\begingroup\$ You should think in terms of RTL - Register Transfer Level. You have registers (the output flip-flop), and cloud logic (the LUTs) that connect the registers together. \$\endgroup\$ Jul 14 '16 at 23:43
  • \$\begingroup\$ @TomCarpenter Not to confuse matters, but some FPGAs will actually let you reconfigure a LUT to be used as memory. For instance, Xilinx parts will expose a LUT as a shift register using the SRL16/SRL32 primitives. \$\endgroup\$
    – user39382
    Jul 14 '16 at 23:50
  • \$\begingroup\$ @duskwuff that's true. Altera FPGAs have MLAB primitives which are the same principle. \$\endgroup\$ Jul 15 '16 at 0:06

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