I began to study CMOS gates, that are in my teacher's book, and I have 2 questions, because there is no explanation.

  1. If we use NAND or NOR , it means we have F = ~(A*B) and F = ~(A+B) and is normal to have that little bubble (negation) at gates A and B right? enter image description here

  2. What if we have function F = A(B+C) + D . Since is not ~(A(B+C) + D) , then why we have that negation bubble at A, B, C gates? Can someone explain please?

enter image description here

  • 1
    \$\begingroup\$ That bubble stands for PMOS transistor symbol. \$\endgroup\$
    – SMA.D
    Jul 15, 2016 at 10:18
  • \$\begingroup\$ aaa, it means positive MOS transistor right? \$\endgroup\$
    – Linksx
    Jul 15, 2016 at 10:19
  • \$\begingroup\$ P channel MOS transistor \$\endgroup\$
    – SMA.D
    Jul 15, 2016 at 10:38

1 Answer 1


That bubble stands for P channel MOSFET transistor. See the following equivalent symbols.

equivalent symbols

See the picture for structure of a P channel MOSFET. In CMOS technology the main substrate is P:


For example in the NAND gate in the question making both A and B HIGH will cause the upper transistors to be OFF and lower transistors to be ON, therefore F is connected to the ground and will be LOW.

  • \$\begingroup\$ as I understand, that bubble will be always there because of P channel , and it won't depend if we have F = ~(AB) or F = (AB), right? \$\endgroup\$
    – Linksx
    Jul 15, 2016 at 10:35
  • \$\begingroup\$ Technically the second image is a depletion-mode MOSFET, which is not commonly used. \$\endgroup\$ Jul 15, 2016 at 10:39
  • \$\begingroup\$ @IgnacioVazquez-Abrams Yes but their concepts are the same . \$\endgroup\$
    – SMA.D
    Jul 15, 2016 at 10:42
  • \$\begingroup\$ @ClaudiuM To create AND gates an additional inverter is required to convert NAND to AND. See this link \$\endgroup\$
    – SMA.D
    Jul 15, 2016 at 10:44
  • \$\begingroup\$ To a point. Specifically to the point that DMOSFETs are normally open. \$\endgroup\$ Jul 15, 2016 at 10:49

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